Lines Matching defs:clock
161 static int tnetd7300_get_clock(u32 shift, struct tnetd7300_clock *clock,
166 u32 ctrl = readl(&clock->ctrl);
167 u32 pll = readl(&clock->pll);
207 static void tnetd7300_set_clock(u32 shift, struct tnetd7300_clock *clock,
230 writel(((prediv - 1) << PREDIV_SHIFT) | (postdiv - 1), &clock->ctrl);
232 writel(4, &clock->pll);
233 while (readl(&clock->pll) & PLL_STATUS)
235 writel(((mul - 1) << MUL_SHIFT) | (0xff << 3) | 0x0e, &clock->pll);
271 static void tnetd7200_set_clock(int base, struct tnetd7200_clock *clock,
279 writel(0, &clock->ctrl);
280 writel(DIVISOR_ENABLE_MASK | ((prediv - 1) & 0x1F), &clock->prediv);
281 writel((mul - 1) & 0xF, &clock->mul);
283 while (readl(&clock->status) & 0x1)
286 writel(DIVISOR_ENABLE_MASK | ((postdiv - 1) & 0x1F), &clock->postdiv);
288 writel(readl(&clock->cmden) | 1, &clock->cmden);
289 writel(readl(&clock->cmd) | 1, &clock->cmd);
291 while (readl(&clock->status) & 0x1)
294 writel(DIVISOR_ENABLE_MASK | ((postdiv2 - 1) & 0x1F), &clock->postdiv2);
296 writel(readl(&clock->cmden) | 1, &clock->cmden);
297 writel(readl(&clock->cmd) | 1, &clock->cmd);
299 while (readl(&clock->status) & 0x1)
302 writel(readl(&clock->ctrl) | 1, &clock->ctrl);
348 printk(KERN_INFO "Clocks: Setting DSP clock\n");
357 printk(KERN_INFO "Clocks: Setting CPU clock\n");
370 printk(KERN_INFO "Clocks: Setting CPU clock\n");
379 printk(KERN_INFO "Clocks: Setting DSP clock\n");
389 printk(KERN_INFO "Clocks: Setting DSP clock\n");
401 printk(KERN_INFO "Clocks: Setting USB clock\n");
434 /* adjust vbus clock rate */