Lines Matching refs:r22
125 shr.u r22=r21,3
133 (p8) shr r22=r22,r27
137 shr.u r18=r22,PGDIR_SHIFT // get bottom portion of pgd index bit
152 shr.u r28=r22,PUD_SHIFT // shift pud index into position
154 shr.u r18=r22,PMD_SHIFT // shift pmd index into position
163 shr.u r18=r22,PMD_SHIFT // shift pmd index into position
173 shr.u r19=r22,PAGE_SHIFT // shift pte index into position
182 MOV_FROM_IHA(r22) // get the VHPT address that caused the TLB miss
190 MOV_TO_IFA(r22, r24)
238 (p6) ptc.l r22,r27 // purge PTE page translation
348 shr.u r22=r16,61 // get the region number into r21
350 cmp.gt p8,p0=6,r22 // user mode
388 shr.u r22=r16,61 // get the region number into r21
390 cmp.gt p8,p0=6,r22 // access to region 0-5
408 and r22=IA64_ISR_CODE_MASK,r20 // get the isr.code field
415 (p9) cmp.eq.or.andcm p6,p7=IA64_ISR_CODE_LFETCH,r22 // check isr.code field
453 * Clobbered: b0, r18, r19, r21, r22, psr.dt (cleared)
464 add r22=-PAGE_SHIFT,r18 // adjustment for hugetlb address
467 shr.u r22=r16,r22
482 shr.u r18=r22,PUD_SHIFT // shift pud index into position
484 shr.u r18=r22,PMD_SHIFT // shift pmd index into position
494 shr.u r18=r22,PMD_SHIFT // shift pmd index into position
501 shr.u r19=r22,PAGE_SHIFT // shift pte index into position
772 addl r22=IA64_RBS_OFFSET,r1 // A compute base of RBS
776 lfetch.fault.excl.nt1 [r22] // M0|1 prefetch RBS
780 mov.m ar.bspstore=r22 // M2 switch to kernel RBS
833 sub r22=r19,r18 // A stime before leave
838 add r20=r20,r22 // A sum stime
917 * - r22: kernel's register backing store base (krbs_base)
978 (pUStk) sub r18=r18,r22 // r18=RSE.ndirty*8
1066 sub r22=r19,r18 // stime before leave kernel
1071 add r23=r23,r22 // sum stime