Lines Matching refs:r17
123 shr.u r17=r16,61 // get the region number into r17
136 cmp.eq p6,p7=5,r17 // is IFA pointing into to region 5?
139 (p7) dep r17=r17,r19,(PAGE_SHIFT-3),3 // put region number bits in place
148 (p6) dep r17=r18,r19,3,(PAGE_SHIFT-3) // r17=pgd_offset for region 5
149 (p7) dep r17=r18,r17,3,(PAGE_SHIFT-6) // r17=pgd_offset for region[0-4]
157 ld8 r17=[r17] // get *pgd (may be 0)
159 (p7) cmp.eq p6,p7=r17,r0 // was pgd_present(*pgd) == NULL?
161 dep r28=r28,r17,3,(PAGE_SHIFT-3) // r28=pud_offset(pgd,addr)
167 dep r17=r18,r29,3,(PAGE_SHIFT-3) // r17=pmd_offset(pud,addr)
169 dep r17=r18,r17,3,(PAGE_SHIFT-3) // r17=pmd_offset(pgd,addr)
172 (p7) ld8 r20=[r17] // get *pmd (may be 0)
218 * r17 = equivalent of pmd_offset(pud, ifa)
226 ld8 r26=[r17] // read *pmd again
263 MOV_FROM_IHA(r17) // get virtual address of PTE
266 1: ld8 r18=[r17] // read *pte
281 ld8 r19=[r17] // read *pte again and see if same
307 MOV_FROM_IHA(r17) // get virtual address of PTE
310 1: ld8 r18=[r17] // read *pte
325 ld8 r19=[r17] // read *pte again and see if same
342 movl r17=PAGE_KERNEL
352 THASH(p8, r17, r16, r23)
354 MOV_TO_IHA(p8, r17, r23)
364 or r19=r17,r19 // insert PTE control bits into r19
380 movl r17=PAGE_KERNEL
392 THASH(p8, r17, r16, r25)
394 MOV_TO_IHA(p8, r17, r25)
416 (p12) dep r17=-1,r17,4,1 // set ma=UC for region 6 addr
421 or r19=r19,r17 // insert PTE control bits into r19
448 * Output: r17: physical address of PTE of faulting address
460 shr.u r17=r16,61 // get the region number into r17
463 cmp.eq p6,p7=5,r17 // is faulting address in region 5?
469 (p7) dep r17=r17,r19,(PAGE_SHIFT-3),3 // put region number bits in place
478 (p6) dep r17=r18,r19,3,(PAGE_SHIFT-3) // r17=pgd_offset for region 5
479 (p7) dep r17=r18,r17,3,(PAGE_SHIFT-6) // r17=pgd_offset for region[0-4]
487 ld8 r17=[r17] // get *pgd (may be 0)
489 (p7) cmp.eq p6,p7=r17,r0 // was pgd_present(*pgd) == NULL?
490 dep r17=r18,r17,3,(PAGE_SHIFT-3) // r17=p[u|m]d_offset(pgd,addr)
493 (p7) ld8 r17=[r17] // get *pud (may be 0)
496 (p7) cmp.eq.or.andcm p6,p7=r17,r0 // was pud_present(*pud) == NULL?
497 dep r17=r18,r17,3,(PAGE_SHIFT-3) // r17=pmd_offset(pud,addr)
500 (p7) ld8 r17=[r17] // get *pmd (may be 0)
503 (p7) cmp.eq.or.andcm p6,p7=r17,r0 // was pmd_present(*pmd) == NULL?
504 dep r17=r19,r17,3,(PAGE_SHIFT-3) // r17=pte_offset(pmd,addr);
543 THASH(p0, r17, r16, r18) // compute virtual address of L3 PTE
549 1: ld8 r18=[r17]
555 (p6) cmpxchg8.acq r26=[r17],r25,ar.ccv // Only update if page is present
568 ld8 r18=[r17] // read PTE again
577 1: ld8 r18=[r17]
582 st8 [r17]=r18 // store back updated PTE
602 MOV_FROM_IPSR(p0, r17)
605 tbit.z p6,p0=r17,IA64_PSR_IS_BIT // IA64 instruction set?
610 THASH(p0, r17, r16, r18) // compute virtual address of L3 PTE
615 1: ld8 r18=[r17]
621 (p6) cmpxchg8.acq r26=[r17],r25,ar.ccv // Only if page present
634 ld8 r18=[r17] // read PTE again
643 1: ld8 r18=[r17]
648 st8 [r17]=r18 // store back updated PTE
664 THASH(p0, r17, r16, r18) // compute virtual address of L3 PTE
670 1: ld8 r18=[r17]
676 (p6) cmpxchg8.acq r26=[r17],r25,ar.ccv // Only if page is present
688 ld8 r18=[r17] // read PTE again
696 1: ld8 r18=[r17]
700 st8 [r17]=r18 // store back updated PTE
732 MOV_FROM_IIM(r17) // M2 (2 cyc)
752 cmp.eq p0,p7=r18,r17 // I0 is this a system call?
767 ld1.bias r17=[r16] // M0|1 r17 = current->thread.on_ustack flag
811 cmp.eq pKStk,pUStk=r0,r17 // A were we on kernel stacks already?
825 add r17=TI_AC_LEAVE+IA64_TASK_SIZE,r13 // A
829 ld8 r19=[r17],TI_AC_UTIME-TI_AC_LEAVE // M time at leave
832 ld8 r21=[r17] // M cumulated utime
842 st8 [r17]=r21 // M update utime
948 add r17=PT(R11),r1 // initialize second base pointer
954 st8.spill [r17]=r11,PT(CR_IIP)-PT(R11) // save r11
960 st8 [r17]=r28,PT(AR_UNAT)-PT(CR_IIP) // save cr.iip
964 st8 [r17]=r25,PT(AR_RSC)-PT(AR_UNAT) // save ar.unat
973 st8 [r17]=r27,PT(AR_BSPSTORE)-PT(AR_RSC)// save ar.rsc
983 (pKStk) adds r17=PT(B0)-PT(AR_BSPSTORE),r17 // skip over ar_bspstore field
991 (pUStk) st8 [r17]=r23,PT(B0)-PT(AR_BSPSTORE) // save ar.bspstore
995 st8 [r17]=r28,PT(R1)-PT(B0) // save b0
999 st8.spill [r17]=r20,PT(R13)-PT(R1) // save original r1
1004 .mem.offset 8,0; st8.spill [r17]=r13,PT(R15)-PT(R13) // save r13
1015 st8.spill [r17]=r15 // save r15
1027 movl r17=FPSR_DEFAULT
1029 mov.m ar.fpsr=r17 // set ar.fpsr to kernel default value
1059 add r17=TI_AC_LEAVE+IA64_TASK_SIZE,r13
1062 ld8 r19=[r17],TI_AC_UTIME-TI_AC_LEAVE // time at left from kernel
1065 ld8 r21=[r17] // cumulated utime
1075 st8 [r17]=r21 // update utime
1114 mov r17=PAGE_SHIFT<<2
1116 ptc.l r16,r17
1197 MOV_FROM_ISR(r17)
1200 and r18=0xf,r17 // r18 = cr.ipsr.code{3:0}
1201 tbit.z p6,p0=r17,IA64_ISR_NA_BIT
1234 MOV_FROM_IIP(r17)
1242 add r17=r17,r18 // now add the offset
1244 MOV_TO_IIP(r17, r19)