Lines Matching refs:r16
73 # define DBG_FAULT(i) mov r16=ar.k2;; shl r16=r16,8;; add r16=(i),r16;;mov ar.k2=r16
113 MOV_FROM_IFA(r16) // get address that caused the TLB miss
122 shl r21=r16,3 // shift bit 60 into sign bit
123 shr.u r17=r16,61 // get the region number into r17
241 (p6) ptc.l r16,r27 // purge translation
259 MOV_FROM_IFA(r16) // get virtual address
286 (p7) ptc.l r16,r20
303 MOV_FROM_IFA(r16) // get virtual address
330 (p7) ptc.l r16,r20
341 MOV_FROM_IFA(r16) // get address that caused the TLB miss
348 shr.u r22=r16,61 // get the region number into r21
352 THASH(p8, r17, r16, r23)
359 and r19=r19,r16 // clear ed, reserved bits, and PTE control bits
360 shr.u r18=r16,57 // move address bit 61 to bit 4
379 MOV_FROM_IFA(r16) // get address that caused the TLB miss
388 shr.u r22=r16,61 // get the region number into r21
392 THASH(p8, r17, r16, r25)
398 cmp.ge p10,p11=r16,r24 // access to per_cpu_data?
399 tbit.z p12,p0=r16,61 // access to region 6?
406 (p11) and r19=r19,r16 // clear non-ppn fields
443 * Input: r16: faulting address
457 shl r21=r16,3 // shift bit 60 into sign bit
460 shr.u r17=r16,61 // get the region number into r17
467 shr.u r22=r16,r22
468 shr.u r18=r16,r18
540 MOV_FROM_IFA(r16) // get the address that caused the fault
543 THASH(p0, r17, r16, r18) // compute virtual address of L3 PTE
572 (p7) ptc.l r16,r24
583 ITC_D(p0, r18, r16) // install updated PTE
595 MOV_FROM_IFA(r16) // get the address that caused the fault
607 (p6) mov r16=r18 // if so, use cr.iip instead of cr.ifa
610 THASH(p0, r17, r16, r18) // compute virtual address of L3 PTE
638 (p7) ptc.l r16,r24
649 ITC_I(p0, r18, r16) // install updated PTE
661 MOV_FROM_IFA(r16) // get the address that caused the fault
664 THASH(p0, r17, r16, r18) // compute virtual address of L3 PTE
692 (p7) ptc.l r16,r24
701 ITC_D(p0, r18, r16) // install updated PTE
728 mov.m r16=IA64_KR(CURRENT) // M2 r16 <- current task (12 cyc)
759 mov r1=r16 // A move task-pointer to "addl"-addressable reg
760 mov r2=r16 // A setup r2 for ia64_syscall_setup
761 add r9=TI_FLAGS+IA64_TASK_SIZE,r16 // A r9 = ¤t_thread_info()->flags
763 adds r16=IA64_TASK_THREAD_ON_USTACK_OFFSET,r16
767 ld1.bias r17=[r16] // M0|1 r17 = current->thread.on_ustack flag
805 st1 [r16]=r0 // M2|3 clear current->thread.on_ustack flag
824 add r16=TI_AC_STAMP+IA64_TASK_SIZE,r13 // A
828 ld8 r18=[r16],TI_AC_STIME-TI_AC_STAMP // M get last stamp
831 ld8 r20=[r16],TI_AC_STAMP-TI_AC_STIME // M cumulated stime
835 st8 [r16]=r30,TI_AC_STIME-TI_AC_STAMP // M update stamp
841 st8 [r16]=r20 // M update stime
851 SSM_PSR_IC_AND_DEFAULT_BITS_AND_SRLZ_I(r3, r16) // M2 now it's safe to re-enable intr.-collection
858 SSM_PSR_I(p15, p15, r16) // M2 restore psr.i
947 add r16=PT(CR_IPSR),r1 // initialize first base pointer
951 st8 [r16]=r29,PT(AR_PFS)-PT(CR_IPSR) // save cr.ipsr
959 st8 [r16]=r26,PT(CR_IFS)-PT(AR_PFS) // save ar.pfs
969 st8 [r16]=r19,PT(AR_RNAT)-PT(CR_IFS) // store ar.pfs.pfm in cr.ifs
982 (pKStk) adds r16=PT(PR)-PT(AR_RNAT),r16 // skip over ar_rnat field
990 (pUStk) st8 [r16]=r24,PT(PR)-PT(AR_RNAT) // save ar.rnat
994 st8 [r16]=r31,PT(LOADRS)-PT(PR) // save predicates
998 st8 [r16]=r18,PT(R12)-PT(LOADRS) // save ar.rsc value for "loadrs"
1003 .mem.offset 0,0; st8.spill [r16]=r12,PT(AR_FPSR)-PT(R12) // save r12
1007 st8 [r16]=r21,PT(R8)-PT(AR_FPSR) // save ar.fpsr
1022 st8 [r16]=r8 // ensure pt_regs.r8 != 0 (see handle_syscall_error)
1058 add r16=TI_AC_STAMP+IA64_TASK_SIZE,r13
1061 ld8 r18=[r16],TI_AC_STIME-TI_AC_STAMP // time at last check in kernel
1064 ld8 r23=[r16],TI_AC_STAMP-TI_AC_STIME // cumulated stime
1068 st8 [r16]=r20,TI_AC_STIME-TI_AC_STAMP // update stamp
1074 st8 [r16]=r23 // update stime
1108 MOV_FROM_IFA(r16)
1116 ptc.l r16,r17
1128 MOV_FROM_IFA(r16)
1141 MOV_FROM_IFA(r16)
1154 MOV_FROM_IFA(r16)
1167 MOV_FROM_ISR(r16)
1170 cmp4.eq p6,p0=0,r16
1196 MOV_FROM_IPSR(p0, r16)
1204 dep r16=-1,r16,IA64_PSR_ED_BIT,1
1207 MOV_TO_IPSR(p0, r16, r18)
1238 MOV_FROM_IPSR(p0, r16)
1245 dep r16=0,r16,41,2 // clear EI
1248 MOV_TO_IPSR(p0, r16, r19)
1519 // call do_page_fault (predicates are in r31, psr.dt may be off, r16 is faulting address)