Lines Matching refs:val
14 static inline void vgic_v2_write_lr(int lr, u32 val)
18 writel_relaxed(val, base + GICH_LR0 + (lr * 4));
60 u32 val = cpuif->vgic_lr[lr];
61 u32 cpuid, intid = val & GICH_LR_VIRTUALID;
66 cpuid = val & GICH_LR_PHYSID_CPUID;
71 if (lr_signals_eoi_mi(val) && vgic_valid_spi(vcpu->kvm, intid))
80 deactivated = irq->active && !(val & GICH_LR_ACTIVE_BIT);
81 irq->active = !!(val & GICH_LR_ACTIVE_BIT);
88 (val & GICH_LR_PENDING_BIT)) {
98 if (irq->config == VGIC_CONFIG_LEVEL && !(val & GICH_LR_STATE))
102 vgic_irq_handle_resampling(irq, deactivated, val & GICH_LR_PENDING_BIT);
124 u32 val = irq->intid;
128 val |= GICH_LR_ACTIVE_BIT;
130 val |= irq->active_source << GICH_LR_PHYSID_CPUID_SHIFT;
133 val |= GICH_LR_EOI;
138 val |= GICH_LR_GROUP1;
141 val |= GICH_LR_HW;
142 val |= irq->hwintid << GICH_LR_PHYSID_CPUID_SHIFT;
152 val |= GICH_LR_EOI;
164 val |= GICH_LR_PENDING_BIT;
176 val |= (src - 1) << GICH_LR_PHYSID_CPUID_SHIFT;
180 val |= GICH_LR_EOI;
191 if (vgic_irq_is_mapped_level(irq) && (val & GICH_LR_PENDING_BIT))
195 val |= (irq->priority >> 3) << GICH_LR_PRIORITY_SHIFT;
197 vcpu->arch.vgic_cpu.vgic_v2.vgic_lr[lr] = val;