Lines Matching refs:val
30 unsigned long val)
36 val &= GENMASK_ULL(len * 8 - 1, 0);
38 return reg | ((u64)val << lower);
106 unsigned long val)
119 dist->enabled = val & GICD_CTLR_ENABLE_SS_G1;
123 val &= ~GICD_CTLR_nASSGIreq;
127 val &= ~GICD_CTLR_nASSGIreq;
128 val |= FIELD_PREP(GICD_CTLR_nASSGIreq, is_hwsgi);
132 dist->nassgireq = val & GICD_CTLR_nASSGIreq;
155 unsigned long val)
162 if (val != vgic_mmio_read_v3_misc(vcpu, addr, len))
167 if ((reg ^ val) & ~GICD_IIDR_REVISION_MASK)
182 val &= ~GICD_CTLR_nASSGIreq;
184 dist->enabled = val & GICD_CTLR_ENABLE_SS_G1;
185 dist->nassgireq = val & GICD_CTLR_nASSGIreq;
189 vgic_mmio_write_v3_misc(vcpu, addr, len, val);
213 unsigned long val)
231 irq->mpidr = val & GENMASK(23, 0);
249 unsigned long val;
251 val = atomic_read(&vgic_cpu->ctlr);
253 val |= GICR_CTLR_IR | GICR_CTLR_CES;
255 return val;
260 unsigned long val)
268 if (!(val & GICR_CTLR_ENABLE_LPIS)) {
358 unsigned long val)
374 irq->pending_latch = test_bit(i, &val);
487 unsigned long val)
499 propbaser = update_64bit_reg(propbaser, addr & 4, len, val);
518 unsigned long val)
530 pendbaser = update_64bit_reg(pendbaser, addr & 4, len, val);
555 unsigned long val)
571 irq = vgic_get_irq(vcpu->kvm, NULL, lower_32_bits(val));
582 unsigned long val)
1153 int offset, u32 *val)
1160 return vgic_uaccess(vcpu, &dev, is_write, offset, val);
1164 int offset, u32 *val)
1171 return vgic_uaccess(vcpu, &rd_dev, is_write, offset, val);
1175 u32 intid, u32 *val)
1181 vgic_write_irq_line_level_info(vcpu, intid, *val);
1183 *val = vgic_read_irq_line_level_info(vcpu, intid);