Lines Matching refs:reg
29 u64 update_64bit_reg(u64 reg, unsigned int offset, unsigned int len,
35 reg &= ~GENMASK_ULL(upper, lower);
38 return reg | ((u64)val << lower);
158 u32 reg;
166 reg = vgic_mmio_read_v3_misc(vcpu, addr, len);
167 if ((reg ^ val) & ~GICD_IIDR_REVISION_MASK)
170 reg = FIELD_GET(GICD_IIDR_REVISION_MASK, reg);
171 switch (reg) {
174 dist->implementation_rev = reg;
429 u64 vgic_sanitise_field(u64 reg, u64 field_mask, int field_shift,
432 u64 field = (reg & field_mask) >> field_shift;
435 return (reg & ~field_mask) | field;
444 static u64 vgic_sanitise_pendbaser(u64 reg)
446 reg = vgic_sanitise_field(reg, GICR_PENDBASER_SHAREABILITY_MASK,
449 reg = vgic_sanitise_field(reg, GICR_PENDBASER_INNER_CACHEABILITY_MASK,
452 reg = vgic_sanitise_field(reg, GICR_PENDBASER_OUTER_CACHEABILITY_MASK,
456 reg &= ~PENDBASER_RES0_MASK;
458 return reg;
461 static u64 vgic_sanitise_propbaser(u64 reg)
463 reg = vgic_sanitise_field(reg, GICR_PROPBASER_SHAREABILITY_MASK,
466 reg = vgic_sanitise_field(reg, GICR_PROPBASER_INNER_CACHEABILITY_MASK,
469 reg = vgic_sanitise_field(reg, GICR_PROPBASER_OUTER_CACHEABILITY_MASK,
473 reg &= ~PROPBASER_RES0_MASK;
474 return reg;
1058 #define SGI_AFFINITY_LEVEL(reg, level) \
1059 ((((reg) & ICC_SGI1R_AFFINITY_## level ##_MASK) \
1065 * @reg: The value written into ICC_{ASGI1,SGI0,SGI1}R by that VCPU
1076 void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg, bool allow_group1)
1087 sgi = (reg & ICC_SGI1R_SGI_ID_MASK) >> ICC_SGI1R_SGI_ID_SHIFT;
1088 broadcast = reg & BIT_ULL(ICC_SGI1R_IRQ_ROUTING_MODE_BIT);
1089 target_cpus = (reg & ICC_SGI1R_TARGET_LIST_MASK) >> ICC_SGI1R_TARGET_LIST_SHIFT;
1090 mpidr = SGI_AFFINITY_LEVEL(reg, 3);
1091 mpidr |= SGI_AFFINITY_LEVEL(reg, 2);
1092 mpidr |= SGI_AFFINITY_LEVEL(reg, 1);