Lines Matching defs:vmcr
278 struct vgic_vmcr vmcr;
281 vgic_get_vmcr(vcpu, &vmcr);
285 val = vmcr.grpen0 << GIC_CPU_CTRL_EnableGrp0_SHIFT;
286 val |= vmcr.grpen1 << GIC_CPU_CTRL_EnableGrp1_SHIFT;
287 val |= vmcr.ackctl << GIC_CPU_CTRL_AckCtl_SHIFT;
288 val |= vmcr.fiqen << GIC_CPU_CTRL_FIQEn_SHIFT;
289 val |= vmcr.cbpr << GIC_CPU_CTRL_CBPR_SHIFT;
290 val |= vmcr.eoim << GIC_CPU_CTRL_EOImodeNS_SHIFT;
301 val = (vmcr.pmr & GICV_PMR_PRIORITY_MASK) >>
305 val = vmcr.bpr;
308 val = vmcr.abpr;
326 struct vgic_vmcr vmcr;
328 vgic_get_vmcr(vcpu, &vmcr);
332 vmcr.grpen0 = !!(val & GIC_CPU_CTRL_EnableGrp0);
333 vmcr.grpen1 = !!(val & GIC_CPU_CTRL_EnableGrp1);
334 vmcr.ackctl = !!(val & GIC_CPU_CTRL_AckCtl);
335 vmcr.fiqen = !!(val & GIC_CPU_CTRL_FIQEn);
336 vmcr.cbpr = !!(val & GIC_CPU_CTRL_CBPR);
337 vmcr.eoim = !!(val & GIC_CPU_CTRL_EOImodeNS);
348 vmcr.pmr = (val << GICV_PMR_PRIORITY_SHIFT) &
352 vmcr.bpr = val;
355 vmcr.abpr = val;
359 vgic_set_vmcr(vcpu, &vmcr);