Lines Matching refs:reset_val
1932 { SYS_DESC(SYS_MDCCINT_EL1), trap_debug_regs, reset_val, MDCCINT_EL1, 0 },
1933 { SYS_DESC(SYS_MDSCR_EL1), trap_debug_regs, reset_val, MDSCR_EL1, 0 },
1951 { SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1, reset_val, OSLSR_EL1,
1964 { SYS_DESC(SYS_DBGVCR32_EL2), NULL, reset_val, DBGVCR32_EL2, 0 },
2061 { SYS_DESC(SYS_SCTLR_EL1), access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 },
2063 { SYS_DESC(SYS_CPACR_EL1), NULL, reset_val, CPACR_EL1, 0 },
2068 { SYS_DESC(SYS_ZCR_EL1), NULL, reset_val, ZCR_EL1, 0, .visibility = sve_visibility },
2074 { SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 },
2075 { SYS_DESC(SYS_TCR2_EL1), access_vm_reg, reset_val, TCR2_EL1, 0 },
2135 { SYS_DESC(SYS_VBAR_EL1), access_rw, reset_val, VBAR_EL1, 0 },
2136 { SYS_DESC(SYS_DISR_EL1), NULL, reset_val, DISR_EL1, 0 },
2151 { SYS_DESC(SYS_CONTEXTIDR_EL1), access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 },
2158 { SYS_DESC(SYS_CNTKCTL_EL1), NULL, reset_val, CNTKCTL_EL1, 0},
2202 .reset = reset_val, .reg = PMUSERENR_EL0, .val = 0 },
2360 .reset = reset_val, .reg = PMCCFILTR_EL0, .val = 0 },
2364 EL2_REG(SCTLR_EL2, access_rw, reset_val, SCTLR_EL2_RES1),
2365 EL2_REG(ACTLR_EL2, access_rw, reset_val, 0),
2366 EL2_REG(HCR_EL2, access_rw, reset_val, 0),
2367 EL2_REG(MDCR_EL2, access_rw, reset_val, 0),
2368 EL2_REG(CPTR_EL2, access_rw, reset_val, CPTR_NVHE_EL2_RES1),
2369 EL2_REG(HSTR_EL2, access_rw, reset_val, 0),
2370 EL2_REG(HFGRTR_EL2, access_rw, reset_val, 0),
2371 EL2_REG(HFGWTR_EL2, access_rw, reset_val, 0),
2372 EL2_REG(HFGITR_EL2, access_rw, reset_val, 0),
2373 EL2_REG(HACR_EL2, access_rw, reset_val, 0),
2375 EL2_REG(HCRX_EL2, access_rw, reset_val, 0),
2377 EL2_REG(TTBR0_EL2, access_rw, reset_val, 0),
2378 EL2_REG(TTBR1_EL2, access_rw, reset_val, 0),
2379 EL2_REG(TCR_EL2, access_rw, reset_val, TCR_EL2_RES1),
2380 EL2_REG(VTTBR_EL2, access_rw, reset_val, 0),
2381 EL2_REG(VTCR_EL2, access_rw, reset_val, 0),
2384 EL2_REG(HDFGRTR_EL2, access_rw, reset_val, 0),
2385 EL2_REG(HDFGWTR_EL2, access_rw, reset_val, 0),
2386 EL2_REG(SPSR_EL2, access_rw, reset_val, 0),
2387 EL2_REG(ELR_EL2, access_rw, reset_val, 0),
2391 EL2_REG(AFSR0_EL2, access_rw, reset_val, 0),
2392 EL2_REG(AFSR1_EL2, access_rw, reset_val, 0),
2393 EL2_REG(ESR_EL2, access_rw, reset_val, 0),
2394 { SYS_DESC(SYS_FPEXC32_EL2), NULL, reset_val, FPEXC32_EL2, 0x700 },
2396 EL2_REG(FAR_EL2, access_rw, reset_val, 0),
2397 EL2_REG(HPFAR_EL2, access_rw, reset_val, 0),
2399 EL2_REG(MAIR_EL2, access_rw, reset_val, 0),
2400 EL2_REG(AMAIR_EL2, access_rw, reset_val, 0),
2402 EL2_REG(VBAR_EL2, access_rw, reset_val, 0),
2403 EL2_REG(RVBAR_EL2, access_rw, reset_val, 0),
2406 EL2_REG(CONTEXTIDR_EL2, access_rw, reset_val, 0),
2407 EL2_REG(TPIDR_EL2, access_rw, reset_val, 0),
2409 EL2_REG(CNTVOFF_EL2, access_rw, reset_val, 0),
2410 EL2_REG(CNTHCTL_EL2, access_rw, reset_val, 0),
2412 EL12_REG(SCTLR, access_vm_reg, reset_val, 0x00C50078),
2413 EL12_REG(CPACR, access_rw, reset_val, 0),
2416 EL12_REG(TCR, access_vm_reg, reset_val, 0),
2425 EL12_REG(VBAR, access_rw, reset_val, 0),
2426 EL12_REG(CONTEXTIDR, access_vm_reg, reset_val, 0),
2427 EL12_REG(CNTKCTL, access_rw, reset_val, 0),