Lines Matching refs:lr_val
485 u64 *lr_val)
513 *lr_val = val;
518 *lr_val = ICC_IAR1_EL1_SPURIOUS;
524 u64 *lr_val)
534 *lr_val = val;
539 *lr_val = ICC_IAR1_EL1_SPURIOUS;
676 u64 lr_val;
682 lr = __vgic_v3_highest_priority_lr(vcpu, vmcr, &lr_val);
686 if (grp != !!(lr_val & ICH_LR_GROUP))
690 lr_prio = (lr_val & ICH_LR_PRIORITY_MASK) >> ICH_LR_PRIORITY_SHIFT;
697 lr_val &= ~ICH_LR_STATE;
698 lr_val |= ICH_LR_ACTIVE_BIT;
699 __gic_v3_set_lr(lr_val, lr);
701 vcpu_set_reg(vcpu, rt, lr_val & ICH_LR_VIRTUAL_ID_MASK);
708 static void __vgic_v3_clear_active_lr(int lr, u64 lr_val)
710 lr_val &= ~ICH_LR_ACTIVE_BIT;
711 if (lr_val & ICH_LR_HW) {
714 pid = (lr_val & ICH_LR_PHYS_ID_MASK) >> ICH_LR_PHYS_ID_SHIFT;
718 __gic_v3_set_lr(lr_val, lr);
733 u64 lr_val;
744 lr = __vgic_v3_find_active_lr(vcpu, vid, &lr_val);
750 __vgic_v3_clear_active_lr(lr, lr_val);
756 u64 lr_val;
765 lr = __vgic_v3_find_active_lr(vcpu, vid, &lr_val);
777 lr_prio = (lr_val & ICH_LR_PRIORITY_MASK) >> ICH_LR_PRIORITY_SHIFT;
780 if (grp != !!(lr_val & ICH_LR_GROUP) ||
785 __vgic_v3_clear_active_lr(lr, lr_val);
935 u64 lr_val;
940 lr = __vgic_v3_highest_priority_lr(vcpu, vmcr, &lr_val);
944 lr_grp = !!(lr_val & ICH_LR_GROUP);
946 lr_val = ICC_IAR1_EL1_SPURIOUS;
949 vcpu_set_reg(vcpu, rt, lr_val & ICH_LR_VIRTUAL_ID_MASK);