Lines Matching refs:and
15 * abort here if the I-TLB and D-TLB aren't seeing the same
23 bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR
33 and r7, r8, #15 << 24
67 and r6, r8, r7
68 and r9, r8, r7, lsl #1
70 and r9, r8, r7, lsl #2
72 and r9, r8, r7, lsl #3
76 and r6, r6, #15 @ r6 = no. of registers to transfer.
77 and r9, r8, #15 << 16 @ Extract 'n' from instruction
91 and r9, r8, #0x00f @ get Rm / low nibble of immediate value
97 and r9, r8, #15 << 16 @ Extract 'n' from instruction
113 and r9, r8, #15 << 16 @ Extract 'n' from instruction
126 and r7, r8, #15 @ Extract 'm' from instruction
131 and r7, r8, #0x70 @ get shift type
173 and r7, r8, #15 << 12
205 and r6, r8, #0x55 @ hweight8(r8) + R bit
206 and r9, r8, #0xaa
208 and r9, r6, #0xcc
209 and r6, r6, #0x33
213 and r6, r6, #15 @ number of regs to transfer
224 and r6, r8, #0x55 @ hweight8(r8)
225 and r9, r8, #0xaa
227 and r9, r6, #0xcc
228 and r6, r6, #0x33
231 and r9, r8, #7 << 8
233 and r6, r6, #15 @ number of regs to transfer