Lines Matching refs:str
64 str \rd, [\tmp]
119 str r2, [r3, r1] @ put flow controller in wait event mode
126 str r1, [r3, #0x340] @ put slave CPU in reset
199 str r1, [r0, #CLK_RESET_SCLK_BURST]
200 str r1, [r0, #CLK_RESET_CCLK_BURST]
202 str r1, [r0, #CLK_RESET_CCLK_DIVIDER]
203 str r1, [r0, #CLK_RESET_SCLK_DIVIDER]
218 str r1, [r7] @ restore the value in pad_save
233 str r4, [r0, #CLK_RESET_SCLK_BURST]
235 str r4, [r0, #CLK_RESET_CCLK_BURST]
240 str r1, [r0, #EMC_CFG]
243 str r1, [r0, #EMC_SELF_REF] @ take DRAM out of self refresh
245 str r1, [r0, #EMC_NOP]
246 str r1, [r0, #EMC_NOP]
256 str r1, [r0, #EMC_REQ_CTRL]
286 str r0, [r5, #CLK_RESET_SCLK_BURST]
287 str r0, [r5, #CLK_RESET_CCLK_BURST]
289 str r0, [r5, #CLK_RESET_CCLK_DIVIDER]
290 str r0, [r5, #CLK_RESET_SCLK_DIVIDER]
305 str r0, [r5, #CLK_RESET_PLLM_BASE]
308 str r0, [r5, #CLK_RESET_PLLP_BASE]
311 str r0, [r5, #CLK_RESET_PLLC_BASE]
315 str r0, [r5, #CLK_RESET_SCLK_BURST]
333 str r0, [r6, r1]
354 str r2, [r1, #EMC_REQ_CTRL] @ stall incoming DRAM requests
362 str r2, [r1, #EMC_SELF_REF]
382 str r1, [r4, r5] @ save the content of the addr
385 str r1, [r0] @ set the save val to the addr
395 str r0, [r2]