Lines Matching defs:base
43 void __iomem *reg = chip->base + 0x08;
58 void __iomem *reg = chip->base + 0x08;
71 void __iomem *reg = chip->base;
106 con = __raw_readl(chip->base);
134 void __iomem *reg = chip->base;
169 void __iomem *reg = chip->base;
238 * base + 0x00: Control register, 2 bits per gpio
241 * base + 0x04: Data register, 1 bit per gpio
248 void __iomem *base = ourchip->base;
254 con = __raw_readl(base + 0x00);
257 __raw_writel(con, base + 0x00);
267 void __iomem *base = ourchip->base;
274 dat = __raw_readl(base + 0x04);
278 __raw_writel(dat, base + 0x04);
280 con = __raw_readl(base + 0x00);
284 __raw_writel(con, base + 0x00);
285 __raw_writel(dat, base + 0x04);
296 * base + 0x00: Control register, 4 bits per gpio
299 * base + 0x04: Data register, 1 bit per gpio
302 * Note, since the data register is one bit per gpio and is at base + 0x4
311 void __iomem *base = ourchip->base;
314 con = __raw_readl(base + GPIOCON_OFF);
319 __raw_writel(con, base + GPIOCON_OFF);
321 pr_debug("%s: %p: CON now %08lx\n", __func__, base, con);
330 void __iomem *base = ourchip->base;
334 con = __raw_readl(base + GPIOCON_OFF);
338 dat = __raw_readl(base + GPIODAT_OFF);
345 __raw_writel(dat, base + GPIODAT_OFF);
346 __raw_writel(con, base + GPIOCON_OFF);
347 __raw_writel(dat, base + GPIODAT_OFF);
349 pr_debug("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
362 * base + 0x00: Control register, 4 bits per gpio (lower 8 GPIOs)
365 * base + 0x04: Control register, 4 bits per gpio (up to 8 additions GPIOs)
368 * base + 0x08: Data register, 1 bit per gpio
372 * routines we store the 'base + 0x4' address so that these routines see
373 * the data register at ourchip->base + 0x04.
380 void __iomem *base = ourchip->base;
381 void __iomem *regcon = base;
393 pr_debug("%s: %p: CON %08lx\n", __func__, base, con);
402 void __iomem *base = ourchip->base;
403 void __iomem *regcon = base;
417 dat = __raw_readl(base + GPIODAT_OFF);
424 __raw_writel(dat, base + GPIODAT_OFF);
426 __raw_writel(dat, base + GPIODAT_OFF);
428 pr_debug("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
437 void __iomem *base = ourchip->base;
443 dat = __raw_readl(base + 0x04);
447 __raw_writel(dat, base + 0x04);
457 val = __raw_readl(ourchip->base + 0x04);
484 gpn = chip->chip.base;
507 BUG_ON(!chip->base);
538 int nr_chips, void __iomem *base,
551 if ((base != NULL) && (chip->base == NULL))
552 chip->base = base + ((i) * offset);
575 int nr_chips, void __iomem *base)
587 if ((base != NULL) && (chip->base == NULL))
588 chip->base = base + ((i) * 0x20);
658 .base = S3C64XX_GPA(0),
664 .base = S3C64XX_GPB(0),
670 .base = S3C64XX_GPC(0),
676 .base = S3C64XX_GPD(0),
683 .base = S3C64XX_GPE(0),
688 .base = S3C64XX_GPG_BASE,
690 .base = S3C64XX_GPG(0),
695 .base = S3C64XX_GPM_BASE,
698 .base = S3C64XX_GPM(0),
708 .base = S3C64XX_GPH_BASE + 0x4,
710 .base = S3C64XX_GPH(0),
715 .base = S3C64XX_GPK_BASE + 0x4,
718 .base = S3C64XX_GPK(0),
723 .base = S3C64XX_GPL_BASE + 0x4,
726 .base = S3C64XX_GPL(0),
736 .base = S3C64XX_GPF_BASE,
739 .base = S3C64XX_GPF(0),
746 .base = S3C64XX_GPI(0),
753 .base = S3C64XX_GPJ(0),
760 .base = S3C64XX_GPO(0),
767 .base = S3C64XX_GPP(0),
774 .base = S3C64XX_GPQ(0),
779 .base = S3C64XX_GPN_BASE,
783 .base = S3C64XX_GPN(0),
830 offset = pin - chip->chip.base;
880 offset = pin - chip->chip.base;