Lines Matching defs:WORK2_REG
16 #define WORK2_REG r1
53 ldr WORK2_REG, [EMCBASE_REG, #LPC32XX_EMC_STATUS_OFFS]
54 and WORK2_REG, WORK2_REG, #LPC32XX_EMC_STATUS_BUSY
55 cmp WORK2_REG, #LPC32XX_EMC_STATUS_BUSY
58 ldr WORK2_REG, [EMCBASE_REG, #LPC32XX_EMC_STATUS_OFFS]
59 and WORK2_REG, WORK2_REG, #LPC32XX_EMC_STATUS_BUSY
60 cmp WORK2_REG, #LPC32XX_EMC_STATUS_BUSY
66 orr WORK2_REG, WORK1_REG, #LPC32XX_CLKPWR_UPD_SDRAM_SELF_RFSH
67 str WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
73 ldr WORK2_REG, [EMCBASE_REG, #LPC32XX_EMC_STATUS_OFFS]
74 and WORK2_REG, WORK2_REG, #LPC32XX_EMC_STATUS_SELF_RFSH
75 cmp WORK2_REG, #LPC32XX_EMC_STATUS_SELF_RFSH
86 and WORK2_REG, SAVED_HCLK_DIV_REG, #CLKPWR_PCLK_DIV_MASK
87 str WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_HCLK_DIV_OFFS]
92 bic WORK2_REG, SAVED_HCLK_PLL_REG, #LPC32XX_CLKPWR_HCLKPLL_POWER_UP
93 str WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS]
109 ldr WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS]
110 and WORK2_REG, WORK2_REG, #LPC32XX_CLKPWR_HCLKPLL_PLL_STS
131 ldr WORK2_REG, [EMCBASE_REG, #LPC32XX_EMC_STATUS_OFFS]
132 and WORK2_REG, WORK2_REG, #LPC32XX_EMC_STATUS_SELF_RFSH