Lines Matching defs:CLKPWRBASE_REG
21 #define CLKPWRBASE_REG r6
43 ldr CLKPWRBASE_REG, [WORK1_REG, #0]
46 ldr SAVED_PWR_CTRL_REG, [CLKPWRBASE_REG,\
65 str WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
67 str WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
68 str WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
80 str WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
84 ldr SAVED_HCLK_DIV_REG, [CLKPWRBASE_REG,\
87 str WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_HCLK_DIV_OFFS]
90 ldr SAVED_HCLK_PLL_REG, [CLKPWRBASE_REG,\
93 str WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS]
97 str WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
106 str SAVED_HCLK_PLL_REG, [CLKPWRBASE_REG,\
109 ldr WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS]
115 str SAVED_PWR_CTRL_REG, [CLKPWRBASE_REG,\
119 str SAVED_HCLK_DIV_REG, [CLKPWRBASE_REG,\
125 str WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
126 str SAVED_PWR_CTRL_REG, [CLKPWRBASE_REG,\