Lines Matching refs:val
58 u32 val;
66 val = readl_relaxed(src_base + SRC_SCR);
67 val |= bit;
68 writel_relaxed(val, src_base + SRC_SCR);
102 u32 val, pup;
106 val = readl_relaxed(gpc_base + reg);
107 val |= BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7;
108 writel_relaxed(val, gpc_base + reg);
115 val &= ~BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7;
116 writel_relaxed(val, gpc_base + reg);
124 u32 mask, val;
133 val = readl_relaxed(src_base + SRC_A7RCR1);
134 val = enable ? val | mask : val & ~mask;
135 writel_relaxed(val, src_base + SRC_A7RCR1);
138 val = readl_relaxed(src_base + SRC_SCR);
139 val = enable ? val | mask : val & ~mask;
140 val |= 1 << (BP_SRC_SCR_CORE1_RST + cpu - 1);
141 writel_relaxed(val, src_base + SRC_SCR);
168 u32 val;
181 val = readl_relaxed(src_base + SRC_SCR);
182 val &= ~(1 << BP_SRC_SCR_WARM_RESET_ENABLE);
183 writel_relaxed(val, src_base + SRC_SCR);