Lines Matching refs:data
35 * struct at91_pm_bu - AT91 power management backup unit data structure
38 * @canary: canary data for memory checking after exit from backup mode
40 * @ddr_phy_calibration: DDR PHY calibration data: ZQ0CR0, first 8 words
115 * struct at91_soc_pm - AT91 SoC power management data structure
119 * @bu: backup unit mapped data (for backup mode)
121 * @data: PM data to be used on last phase of suspend
131 struct at91_pm_data data;
151 .data = {
167 __raw_readl(soc_pm.data.ramc[id] + field)
170 __raw_writel(value, soc_pm.data.ramc[id] + field)
203 { .compatible = "atmel,sama5d2-gem", .data = &ws_info[0] },
204 { .compatible = "atmel,sama5d2-rtc", .data = &ws_info[1] },
205 { .compatible = "atmel,sama5d3-udc", .data = &ws_info[2] },
206 { .compatible = "atmel,at91rm9200-ohci", .data = &ws_info[2] },
207 { .compatible = "usb-ohci", .data = &ws_info[2] },
208 { .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] },
209 { .compatible = "usb-ehci", .data = &ws_info[2] },
210 { .compatible = "atmel,sama5d2-sdhci", .data = &ws_info[3] },
215 { .compatible = "microchip,sam9x60-rtc", .data = &ws_info[1] },
216 { .compatible = "atmel,at91rm9200-ohci", .data = &ws_info[2] },
217 { .compatible = "usb-ohci", .data = &ws_info[2] },
218 { .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] },
219 { .compatible = "usb-ehci", .data = &ws_info[2] },
220 { .compatible = "microchip,sam9x60-rtt", .data = &ws_info[4] },
221 { .compatible = "cdns,sam9x60-macb", .data = &ws_info[5] },
226 { .compatible = "microchip,sama7g5-rtc", .data = &ws_info[1] },
227 { .compatible = "microchip,sama7g5-ohci", .data = &ws_info[2] },
228 { .compatible = "usb-ohci", .data = &ws_info[2] },
229 { .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] },
230 { .compatible = "usb-ehci", .data = &ws_info[2] },
231 { .compatible = "microchip,sama7g5-sdhci", .data = &ws_info[3] },
232 { .compatible = "microchip,sama7g5-rtt", .data = &ws_info[4] },
247 if (!soc_pm.data.pmc || !soc_pm.data.shdwc || !soc_pm.ws_ids)
251 writel(mode, soc_pm.data.pmc + AT91_PMC_FSMR);
256 soc_pm.config_shdwc_ws(soc_pm.data.shdwc, &mode, &polarity);
259 val = readl(soc_pm.data.shdwc + 0x04);
268 wsi = match->data;
285 soc_pm.config_pmc_ws(soc_pm.data.pmc, mode, polarity);
330 if (!(eth->modes & BIT(soc_pm.data.mode)))
376 if (suspend && eth->dns_modes & BIT(soc_pm.data.mode)) {
463 soc_pm.data.mode = soc_pm.data.suspend_mode;
467 soc_pm.data.mode = soc_pm.data.standby_mode;
471 soc_pm.data.mode = -1;
474 ret = at91_pm_config_ws(soc_pm.data.mode, true);
478 if (soc_pm.data.mode == AT91_PM_BACKUP)
495 scsr = readl(soc_pm.data.pmc + AT91_PMC_SCSR);
498 if ((scsr & soc_pm.data.uhp_udp_mask) != 0) {
509 css = readl(soc_pm.data.pmc + AT91_PMC_PCKR(i)) & AT91_PMC_CSS;
531 return (soc_pm.data.mode >= AT91_PM_ULP0);
550 if (soc_pm.data.mode == AT91_PM_BACKUP && soc_pm.data.ramc_phy) {
558 tmp = readl(soc_pm.data.ramc_phy + DDR3PHY_ZQ0SR0);
589 at91_suspend_sram_fn(&soc_pm.data);
600 if (!soc_pm.data.sfrbu)
603 val = readl(soc_pm.data.sfrbu + offset);
611 writel(val, soc_pm.data.sfrbu + offset);
614 val = readl(soc_pm.data.sfrbu + offset);
616 val = readl(soc_pm.data.sfrbu + offset);
621 if (soc_pm.data.mode == AT91_PM_BACKUP) {
662 if (soc_pm.data.mode >= AT91_PM_ULP0 &&
689 at91_pm_config_ws(soc_pm.data.mode, false);
722 : "r" (0), "r" (soc_pm.data.ramc[0]),
745 if (soc_pm.data.ramc[1]) {
763 if (soc_pm.data.ramc[1])
770 if (soc_pm.data.ramc[1]) {
800 if (soc_pm.data.ramc[1]) {
812 if (soc_pm.data.ramc[1])
818 if (soc_pm.data.ramc[1])
826 pwrtmg = readl(soc_pm.data.ramc[0] + UDDRC_PWRCTL);
827 ratio = readl(soc_pm.data.pmc + AT91_PMC_RATIO);
835 soc_pm.data.ramc[0] + UDDRC_PWRCTL);
837 writel(ratio & ~AT91_PMC_RATIO_RATIO, soc_pm.data.pmc + AT91_PMC_RATIO);
842 writel(ratio, soc_pm.data.pmc + AT91_PMC_RATIO);
843 writel(pwrtmg, soc_pm.data.ramc[0] + UDDRC_PWRCTL);
860 { .compatible = "atmel,at91rm9200-sdramc", .data = &ramc_infos[0] },
861 { .compatible = "atmel,at91sam9260-sdramc", .data = &ramc_infos[1] },
862 { .compatible = "atmel,at91sam9g45-ddramc", .data = &ramc_infos[2] },
863 { .compatible = "atmel,sama5d3-ddramc", .data = &ramc_infos[3] },
864 { .compatible = "microchip,sama7g5-uddrc", .data = &ramc_infos[4], },
883 soc_pm.data.ramc[idx] = of_iomap(np, 0);
884 if (!soc_pm.data.ramc[idx]) {
891 ramc = of_id->data;
895 soc_pm.data.memctrl = ramc->memctrl;
909 soc_pm.data.ramc_phy = of_iomap(np, 0);
910 if (!soc_pm.data.ramc_phy) {
918 if (phy_mandatory && !soc_pm.data.ramc_phy) {
935 iounmap(soc_pm.data.ramc[--idx]);
946 writel(AT91_PMC_PCK, soc_pm.data.pmc + AT91_PMC_SCDR);
951 writel(AT91_PMC_PCK, soc_pm.data.pmc + AT91_PMC_SCDR);
1008 return (soc_pm.data.standby_mode == pm_mode ||
1009 soc_pm.data.suspend_mode == pm_mode);
1014 void *data)
1018 int *located = data;
1081 if (soc_pm.data.ramc_phy) {
1099 suspend_mode = soc_pm.data.suspend_mode;
1121 soc_pm.data.suspend_mode = res.a1;
1190 (soc_pm.data.standby_mode), \
1191 (soc_pm.data.suspend_mode)); \
1193 (soc_pm.data.suspend_mode), \
1194 (soc_pm.data.standby_mode)); \
1226 if (soc_pm.data.standby_mode == AT91_PM_BACKUP)
1227 soc_pm.data.standby_mode = AT91_PM_ULP0;
1228 if (soc_pm.data.suspend_mode == AT91_PM_BACKUP)
1229 soc_pm.data.suspend_mode = AT91_PM_ULP0;
1232 if (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SHDWC) ||
1233 maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SHDWC)) {
1239 soc_pm.data.shdwc = of_iomap(np, 0);
1244 if (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SFRBU) ||
1245 maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SFRBU)) {
1251 soc_pm.data.sfrbu = of_iomap(np, 0);
1259 (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(ETHC) ||
1260 maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(ETHC))) {
1292 if (soc_pm.data.shdwc &&
1293 !(maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SHDWC) ||
1294 maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SHDWC))) {
1295 iounmap(soc_pm.data.shdwc);
1296 soc_pm.data.shdwc = NULL;
1299 if (soc_pm.data.sfrbu &&
1300 !(maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SFRBU) ||
1301 maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SFRBU))) {
1302 iounmap(soc_pm.data.sfrbu);
1303 soc_pm.data.sfrbu = NULL;
1349 { .compatible = "atmel,at91rm9200-pmc", .data = &pmc_infos[0] },
1350 { .compatible = "atmel,at91sam9260-pmc", .data = &pmc_infos[1] },
1351 { .compatible = "atmel,at91sam9261-pmc", .data = &pmc_infos[1] },
1352 { .compatible = "atmel,at91sam9263-pmc", .data = &pmc_infos[1] },
1353 { .compatible = "atmel,at91sam9g45-pmc", .data = &pmc_infos[2] },
1354 { .compatible = "atmel,at91sam9n12-pmc", .data = &pmc_infos[1] },
1355 { .compatible = "atmel,at91sam9rl-pmc", .data = &pmc_infos[3] },
1356 { .compatible = "atmel,at91sam9x5-pmc", .data = &pmc_infos[1] },
1357 { .compatible = "atmel,sama5d3-pmc", .data = &pmc_infos[1] },
1358 { .compatible = "atmel,sama5d4-pmc", .data = &pmc_infos[1] },
1359 { .compatible = "atmel,sama5d2-pmc", .data = &pmc_infos[1] },
1360 { .compatible = "microchip,sam9x60-pmc", .data = &pmc_infos[4] },
1361 { .compatible = "microchip,sama7g5-pmc", .data = &pmc_infos[5] },
1374 if (modes[i] == soc_pm.data.standby_mode && !standby) {
1379 if (modes[i] == soc_pm.data.suspend_mode && !suspend) {
1386 if (soc_pm.data.suspend_mode == AT91_PM_STANDBY)
1392 pm_modes[soc_pm.data.standby_mode].pattern,
1394 soc_pm.data.standby_mode = mode;
1398 if (soc_pm.data.standby_mode == AT91_PM_ULP0)
1404 pm_modes[soc_pm.data.suspend_mode].pattern,
1406 soc_pm.data.suspend_mode = mode;
1420 soc_pm.data.pmc = of_iomap(pmc_np, 0);
1422 if (!soc_pm.data.pmc) {
1427 pmc = of_id->data;
1428 soc_pm.data.uhp_udp_mask = pmc->uhp_udp_mask;
1429 soc_pm.data.pmc_mckr_offset = pmc->mckr;
1430 soc_pm.data.pmc_version = pmc->version;
1440 pm_modes[soc_pm.data.standby_mode].pattern,
1441 pm_modes[soc_pm.data.suspend_mode].pattern);
1459 soc_pm.data.standby_mode = AT91_PM_STANDBY;
1460 soc_pm.data.suspend_mode = AT91_PM_ULP0;
1511 soc_pm.data.standby_mode = AT91_PM_STANDBY;
1512 soc_pm.data.suspend_mode = AT91_PM_ULP0;
1664 soc_pm.data.standby_mode = standby;
1665 soc_pm.data.suspend_mode = suspend;