Lines Matching defs:soc_pm
150 static struct at91_soc_pm soc_pm = {
167 __raw_readl(soc_pm.data.ramc[id] + field)
170 __raw_writel(value, soc_pm.data.ramc[id] + field)
247 if (!soc_pm.data.pmc || !soc_pm.data.shdwc || !soc_pm.ws_ids)
251 writel(mode, soc_pm.data.pmc + AT91_PMC_FSMR);
255 if (soc_pm.config_shdwc_ws)
256 soc_pm.config_shdwc_ws(soc_pm.data.shdwc, &mode, &polarity);
259 val = readl(soc_pm.data.shdwc + 0x04);
262 for_each_matching_node_and_match(np, soc_pm.ws_ids, &match) {
284 if (soc_pm.config_pmc_ws)
285 soc_pm.config_pmc_ws(soc_pm.data.pmc, mode, polarity);
330 if (!(eth->modes & BIT(soc_pm.data.mode)))
356 * soc_pm.quirks.eth[].np cannot handle WoL packets while in ULP0, ULP1
365 eth = &soc_pm.quirks.eth[i];
376 if (suspend && eth->dns_modes & BIT(soc_pm.data.mode)) {
431 eth = &soc_pm.quirks.eth[j];
463 soc_pm.data.mode = soc_pm.data.suspend_mode;
467 soc_pm.data.mode = soc_pm.data.standby_mode;
471 soc_pm.data.mode = -1;
474 ret = at91_pm_config_ws(soc_pm.data.mode, true);
478 if (soc_pm.data.mode == AT91_PM_BACKUP)
479 soc_pm.bu->suspended = 1;
480 else if (soc_pm.bu)
481 soc_pm.bu->suspended = 0;
495 scsr = readl(soc_pm.data.pmc + AT91_PMC_SCSR);
498 if ((scsr & soc_pm.data.uhp_udp_mask) != 0) {
509 css = readl(soc_pm.data.pmc + AT91_PMC_PCKR(i)) & AT91_PMC_CSS;
531 return (soc_pm.data.mode >= AT91_PM_ULP0);
550 if (soc_pm.data.mode == AT91_PM_BACKUP && soc_pm.data.ramc_phy) {
558 tmp = readl(soc_pm.data.ramc_phy + DDR3PHY_ZQ0SR0);
562 soc_pm.bu->ddr_phy_calibration[0] = modified_gray_code[index];
566 soc_pm.bu->ddr_phy_calibration[0] |= modified_gray_code[index];
570 soc_pm.bu->ddr_phy_calibration[0] |= modified_gray_code[index];
574 soc_pm.bu->ddr_phy_calibration[0] |= modified_gray_code[index];
582 soc_pm.bu->ddr_phy_calibration[i] =
583 *((unsigned int *)soc_pm.memcs + (i - 1));
589 at91_suspend_sram_fn(&soc_pm.data);
600 if (!soc_pm.data.sfrbu)
603 val = readl(soc_pm.data.sfrbu + offset);
606 if (!(val & soc_pm.sfrbu_regs.pswbu.state))
609 val &= ~soc_pm.sfrbu_regs.pswbu.softsw;
610 val |= soc_pm.sfrbu_regs.pswbu.key | soc_pm.sfrbu_regs.pswbu.ctrl;
611 writel(val, soc_pm.data.sfrbu + offset);
614 val = readl(soc_pm.data.sfrbu + offset);
615 while (val & soc_pm.sfrbu_regs.pswbu.state)
616 val = readl(soc_pm.data.sfrbu + offset);
621 if (soc_pm.data.mode == AT91_PM_BACKUP) {
662 if (soc_pm.data.mode >= AT91_PM_ULP0 &&
689 at91_pm_config_ws(soc_pm.data.mode, false);
722 : "r" (0), "r" (soc_pm.data.ramc[0]),
745 if (soc_pm.data.ramc[1]) {
763 if (soc_pm.data.ramc[1])
770 if (soc_pm.data.ramc[1]) {
800 if (soc_pm.data.ramc[1]) {
812 if (soc_pm.data.ramc[1])
818 if (soc_pm.data.ramc[1])
826 pwrtmg = readl(soc_pm.data.ramc[0] + UDDRC_PWRCTL);
827 ratio = readl(soc_pm.data.pmc + AT91_PMC_RATIO);
835 soc_pm.data.ramc[0] + UDDRC_PWRCTL);
837 writel(ratio & ~AT91_PMC_RATIO_RATIO, soc_pm.data.pmc + AT91_PMC_RATIO);
842 writel(ratio, soc_pm.data.pmc + AT91_PMC_RATIO);
843 writel(pwrtmg, soc_pm.data.ramc[0] + UDDRC_PWRCTL);
883 soc_pm.data.ramc[idx] = of_iomap(np, 0);
884 if (!soc_pm.data.ramc[idx]) {
895 soc_pm.data.memctrl = ramc->memctrl;
909 soc_pm.data.ramc_phy = of_iomap(np, 0);
910 if (!soc_pm.data.ramc_phy) {
918 if (phy_mandatory && !soc_pm.data.ramc_phy) {
935 iounmap(soc_pm.data.ramc[--idx]);
946 writel(AT91_PMC_PCK, soc_pm.data.pmc + AT91_PMC_SCDR);
951 writel(AT91_PMC_PCK, soc_pm.data.pmc + AT91_PMC_SCDR);
1008 return (soc_pm.data.standby_mode == pm_mode ||
1009 soc_pm.data.suspend_mode == pm_mode);
1033 soc_pm.memcs = __va((phys_addr_t)be32_to_cpu(*reg));
1071 soc_pm.bu = (void *)gen_pool_alloc(sram_pool, sizeof(struct at91_pm_bu));
1072 if (!soc_pm.bu) {
1078 soc_pm.bu->suspended = 0;
1079 soc_pm.bu->canary = __pa_symbol(&canary);
1080 soc_pm.bu->resume = __pa_symbol(cpu_resume);
1081 if (soc_pm.data.ramc_phy) {
1099 suspend_mode = soc_pm.data.suspend_mode;
1121 soc_pm.data.suspend_mode = res.a1;
1190 (soc_pm.data.standby_mode), \
1191 (soc_pm.data.suspend_mode)); \
1193 (soc_pm.data.suspend_mode), \
1194 (soc_pm.data.standby_mode)); \
1219 struct at91_pm_quirk_eth *gmac = &soc_pm.quirks.eth[AT91_PM_G_ETH];
1220 struct at91_pm_quirk_eth *emac = &soc_pm.quirks.eth[AT91_PM_E_ETH];
1226 if (soc_pm.data.standby_mode == AT91_PM_BACKUP)
1227 soc_pm.data.standby_mode = AT91_PM_ULP0;
1228 if (soc_pm.data.suspend_mode == AT91_PM_BACKUP)
1229 soc_pm.data.suspend_mode = AT91_PM_ULP0;
1232 if (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SHDWC) ||
1233 maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SHDWC)) {
1239 soc_pm.data.shdwc = of_iomap(np, 0);
1244 if (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SFRBU) ||
1245 maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SFRBU)) {
1251 soc_pm.data.sfrbu = of_iomap(np, 0);
1259 (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(ETHC) ||
1260 maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(ETHC))) {
1292 if (soc_pm.data.shdwc &&
1293 !(maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SHDWC) ||
1294 maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SHDWC))) {
1295 iounmap(soc_pm.data.shdwc);
1296 soc_pm.data.shdwc = NULL;
1299 if (soc_pm.data.sfrbu &&
1300 !(maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SFRBU) ||
1301 maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SFRBU))) {
1302 iounmap(soc_pm.data.sfrbu);
1303 soc_pm.data.sfrbu = NULL;
1374 if (modes[i] == soc_pm.data.standby_mode && !standby) {
1379 if (modes[i] == soc_pm.data.suspend_mode && !suspend) {
1386 if (soc_pm.data.suspend_mode == AT91_PM_STANDBY)
1392 pm_modes[soc_pm.data.standby_mode].pattern,
1394 soc_pm.data.standby_mode = mode;
1398 if (soc_pm.data.standby_mode == AT91_PM_ULP0)
1404 pm_modes[soc_pm.data.suspend_mode].pattern,
1406 soc_pm.data.suspend_mode = mode;
1420 soc_pm.data.pmc = of_iomap(pmc_np, 0);
1422 if (!soc_pm.data.pmc) {
1428 soc_pm.data.uhp_udp_mask = pmc->uhp_udp_mask;
1429 soc_pm.data.pmc_mckr_offset = pmc->mckr;
1430 soc_pm.data.pmc_version = pmc->version;
1440 pm_modes[soc_pm.data.standby_mode].pattern,
1441 pm_modes[soc_pm.data.suspend_mode].pattern);
1459 soc_pm.data.standby_mode = AT91_PM_STANDBY;
1460 soc_pm.data.suspend_mode = AT91_PM_ULP0;
1495 soc_pm.ws_ids = sam9x60_ws_ids;
1496 soc_pm.config_pmc_ws = at91_sam9x60_config_pmc_ws;
1511 soc_pm.data.standby_mode = AT91_PM_STANDBY;
1512 soc_pm.data.suspend_mode = AT91_PM_ULP0;
1544 soc_pm.quirks.eth[AT91_PM_G_ETH].modes = BIT(AT91_PM_ULP0) |
1548 soc_pm.quirks.eth[AT91_PM_G_ETH].dns_modes = BIT(AT91_PM_ULP0) |
1585 soc_pm.ws_ids = sama5d2_ws_ids;
1586 soc_pm.config_shdwc_ws = at91_sama5d2_config_shdwc_ws;
1587 soc_pm.config_pmc_ws = at91_sama5d2_config_pmc_ws;
1589 soc_pm.sfrbu_regs.pswbu.key = (0x4BD20C << 8);
1590 soc_pm.sfrbu_regs.pswbu.ctrl = BIT(0);
1591 soc_pm.sfrbu_regs.pswbu.softsw = BIT(1);
1592 soc_pm.sfrbu_regs.pswbu.state = BIT(3);
1595 soc_pm.quirks.eth[AT91_PM_G_ETH].modes = BIT(AT91_PM_ULP0) |
1602 soc_pm.quirks.eth[AT91_PM_G_ETH].dns_modes = BIT(AT91_PM_ULP0) |
1633 soc_pm.ws_ids = sama7g5_ws_ids;
1634 soc_pm.config_pmc_ws = at91_sam9x60_config_pmc_ws;
1636 soc_pm.sfrbu_regs.pswbu.key = (0x4BD20C << 8);
1637 soc_pm.sfrbu_regs.pswbu.ctrl = BIT(0);
1638 soc_pm.sfrbu_regs.pswbu.softsw = BIT(1);
1639 soc_pm.sfrbu_regs.pswbu.state = BIT(2);
1642 soc_pm.quirks.eth[AT91_PM_E_ETH].modes = BIT(AT91_PM_ULP1);
1643 soc_pm.quirks.eth[AT91_PM_G_ETH].modes = BIT(AT91_PM_ULP1);
1664 soc_pm.data.standby_mode = standby;
1665 soc_pm.data.suspend_mode = suspend;