Lines Matching defs:counter
3 * ARMv6 Performance counter handling code.
7 * ARMv6 has 2 configurable performance counters and a single cycle counter.
16 * the event bus. The procedure for disabling a configurable counter is:
17 * - change the counter to count the ETMEXTOUT[0] signal (0x20). This
18 * effectively stops the counter from counting.
19 * - disable the counter's interrupt generation (each counter has it's
21 * Once stopped, the counter value can be written as 0 to reset.
23 * To enable a counter:
24 * - enable the counter's interrupt generation.
27 * Note: the dedicated cycle counter only counts cycles and can't be
29 * cycle counter, we have to just disable the interrupt reporting and start
30 * ignoring that counter. When re-enabling, we have to reset the value and
107 * can use a raw counter.
170 * can use a raw counter.
220 enum armv6_counters counter)
224 if (ARMV6_CYCLE_COUNTER == counter)
226 else if (ARMV6_COUNTER0 == counter)
228 else if (ARMV6_COUNTER1 == counter)
231 WARN_ONCE(1, "invalid counter number (%d)\n", counter);
239 int counter = hwc->idx;
242 if (ARMV6_CYCLE_COUNTER == counter)
244 else if (ARMV6_COUNTER0 == counter)
246 else if (ARMV6_COUNTER1 == counter)
249 WARN_ONCE(1, "invalid counter number (%d)\n", counter);
257 int counter = hwc->idx;
259 if (ARMV6_CYCLE_COUNTER == counter)
261 else if (ARMV6_COUNTER0 == counter)
263 else if (ARMV6_COUNTER1 == counter)
266 WARN_ONCE(1, "invalid counter number (%d)\n", counter);
289 WARN_ONCE(1, "invalid counter number (%d)\n", idx);
294 * Mask out the current event and set the counter to count the event
336 * each counter has overflowed before we process it.
392 /* Always place a cycle counter into the cycle counter. */
400 * For anything other than a cycle counter, try and use
438 WARN_ONCE(1, "invalid counter number (%d)\n", idx);
443 * Mask out the current event and set the counter to count the number
470 WARN_ONCE(1, "invalid counter number (%d)\n", idx);