Lines Matching refs:write_aux_reg
221 write_aux_reg(aux_tag, paddr);
231 write_aux_reg(ARC_REG_IC_PTAG_HI, (u64)paddr >> 32);
235 write_aux_reg(aux_tag, paddr);
239 write_aux_reg(aux_cmd, vaddr);
286 write_aux_reg(ARC_REG_IC_PTAG_HI, (u64)paddr >> 32);
288 write_aux_reg(ARC_REG_DC_PTAG_HI, (u64)paddr >> 32);
292 write_aux_reg(aux_cmd, paddr);
332 write_aux_reg(ARC_REG_IC_PTAG_HI, (u64)paddr >> 32);
334 write_aux_reg(ARC_REG_DC_PTAG_HI, (u64)paddr >> 32);
338 write_aux_reg(e, paddr + sz); /* ENDR is exclusive */
339 write_aux_reg(s, paddr);
372 write_aux_reg(ctl, read_aux_reg(ctl) | DC_CTRL_INV_MODE_FLUSH);
396 write_aux_reg(ctl, val);
414 write_aux_reg(ctl, reg & ~DC_CTRL_INV_MODE_FLUSH);
435 write_aux_reg(aux, 0x1);
445 write_aux_reg(r, read_aux_reg(r) | DC_CTRL_DIS);
452 write_aux_reg(r, read_aux_reg(r) & ~DC_CTRL_DIS);
492 write_aux_reg(ARC_REG_IC_IVIC, 1);
583 write_aux_reg(ARC_REG_SLC_CTRL, ctrl);
592 write_aux_reg(ARC_REG_SLC_RGN_END1, upper_32_bits(end));
594 write_aux_reg(ARC_REG_SLC_RGN_END, lower_32_bits(end));
597 write_aux_reg(ARC_REG_SLC_RGN_START1, upper_32_bits(paddr));
599 write_aux_reg(ARC_REG_SLC_RGN_START, lower_32_bits(paddr));
637 write_aux_reg(ARC_REG_SLC_CTRL, ctrl);
647 write_aux_reg(cmd, paddr);
673 write_aux_reg(r, ctrl);
676 write_aux_reg(ARC_REG_SLC_INVALIDATE, 0x1);
678 write_aux_reg(ARC_REG_SLC_FLUSH, 0x1);
692 write_aux_reg(r, read_aux_reg(r) | SLC_CTRL_DIS);
699 write_aux_reg(r, read_aux_reg(r) & ~SLC_CTRL_DIS);
1087 write_aux_reg(ARC_REG_IO_COH_AP0_SIZE, order_base_2(mem_sz >> 10) - 2);
1095 write_aux_reg(ARC_REG_IO_COH_AP0_BASE, ioc_base >> 12);
1096 write_aux_reg(ARC_REG_IO_COH_PARTIAL, ARC_IO_COH_PARTIAL_BIT);
1097 write_aux_reg(ARC_REG_IO_COH_ENABLE, ARC_IO_COH_ENABLE_BIT);
1208 write_aux_reg(ARC_REG_IC_PTAG_HI, 0);
1211 write_aux_reg(ARC_REG_DC_PTAG_HI, 0);
1214 write_aux_reg(ARC_REG_SLC_RGN_END1, 0);
1215 write_aux_reg(ARC_REG_SLC_RGN_START1, 0);