Lines Matching refs:regx
251 intelhaddata->aud_config.regx.aud_en = enable;
287 ch_stat0.regx.lpcm_id = (intelhaddata->aes_bits &
289 ch_stat0.regx.clk_acc = (intelhaddata->aes_bits &
294 ch_stat0.regx.samp_freq = CH_STATUS_MAP_32KHZ;
298 ch_stat0.regx.samp_freq = CH_STATUS_MAP_44KHZ;
301 ch_stat0.regx.samp_freq = CH_STATUS_MAP_48KHZ;
304 ch_stat0.regx.samp_freq = CH_STATUS_MAP_88KHZ;
307 ch_stat0.regx.samp_freq = CH_STATUS_MAP_96KHZ;
310 ch_stat0.regx.samp_freq = CH_STATUS_MAP_176KHZ;
313 ch_stat0.regx.samp_freq = CH_STATUS_MAP_192KHZ;
326 ch_stat1.regx.max_wrd_len = MAX_SMPL_WIDTH_20;
327 ch_stat1.regx.wrd_len = SMPL_WIDTH_16BITS;
331 ch_stat1.regx.max_wrd_len = MAX_SMPL_WIDTH_24;
332 ch_stat1.regx.wrd_len = SMPL_WIDTH_24BITS;
357 buf_cfg.regx.audio_fifo_watermark = FIFO_THRESHOLD;
358 buf_cfg.regx.dma_fifo_watermark = DMA_FIFO_THRESHOLD;
359 buf_cfg.regx.aud_delay = 0;
363 cfg_val.regx.num_ch = channels - 2;
365 cfg_val.regx.layout = LAYOUT0;
367 cfg_val.regx.layout = LAYOUT1;
370 cfg_val.regx.packet_mode = 1;
373 cfg_val.regx.left_align = 1;
375 cfg_val.regx.val_bit = 1;
379 cfg_val.regx.dp_modei = 1;
380 cfg_val.regx.set = 1;
611 frame2.regx.chnl_cnt = substream->runtime->channels - 1;
612 frame3.regx.chnl_alloc = ca;
622 frame2.regx.chksum = -(checksum);
633 ctrl_state.regx.dip_freq = 1;
634 ctrl_state.regx.dip_en_sta = 1;