Lines Matching defs:dbri
8 * Based entirely upon drivers/sbus/audio/dbri.c which is:
310 void __iomem *regs; /* dbri HW regs */
571 #define DBRI_STREAM(dbri, substream) \
572 &dbri->stream_info[DBRI_STREAMNO(substream)]
629 dbri->dma->cmd buffer. After this, the commands can be written to
639 static void dbri_cmdwait(struct snd_dbri *dbri)
645 spin_lock_irqsave(&dbri->lock, flags);
646 while ((--maxloops) > 0 && (sbus_readl(dbri->regs + REG0) & D_P)) {
647 spin_unlock_irqrestore(&dbri->lock, flags);
649 spin_lock_irqsave(&dbri->lock, flags);
651 spin_unlock_irqrestore(&dbri->lock, flags);
663 static s32 *dbri_cmdlock(struct snd_dbri *dbri, int len)
665 u32 dvma_addr = (u32)dbri->dma_dvma;
669 spin_lock(&dbri->cmdlock);
670 if (dbri->cmdptr - dbri->dma->cmd + len < DBRI_NO_CMDS - 2)
671 return dbri->cmdptr + 2;
672 else if (len < sbus_readl(dbri->regs + REG8) - dvma_addr)
673 return dbri->dma->cmd;
688 static void dbri_cmdsend(struct snd_dbri *dbri, s32 *cmd, int len)
690 u32 dvma_addr = (u32)dbri->dma_dvma;
700 addr = dvma_addr + (cmd - len - dbri->dma->cmd) * sizeof(s32);
701 *(dbri->cmdptr+1) = addr;
702 *(dbri->cmdptr) = DBRI_CMD(D_JUMP, 0, 0);
705 if (cmd > dbri->cmdptr) {
708 for (ptr = dbri->cmdptr; ptr < cmd+2; ptr++)
712 s32 *ptr = dbri->cmdptr;
717 for (ptr = dbri->dma->cmd; ptr < cmd+2; ptr++)
724 tmp = sbus_readl(dbri->regs + REG0);
726 sbus_writel(tmp, dbri->regs + REG0);
728 dbri->cmdptr = cmd;
729 spin_unlock(&dbri->cmdlock);
733 static void dbri_reset(struct snd_dbri *dbri)
739 sbus_readl(dbri->regs + REG0),
740 sbus_readl(dbri->regs + REG2),
741 sbus_readl(dbri->regs + REG8), sbus_readl(dbri->regs + REG9));
743 sbus_writel(D_R, dbri->regs + REG0); /* Soft Reset */
744 for (i = 0; (sbus_readl(dbri->regs + REG0) & D_R) && i < 64; i++)
749 tmp = sbus_readl(dbri->regs + REG0);
752 sbus_writel(tmp, dbri->regs + REG0);
756 static void dbri_initialize(struct snd_dbri *dbri)
758 u32 dvma_addr = (u32)dbri->dma_dvma;
764 spin_lock_irqsave(&dbri->lock, flags);
766 dbri_reset(dbri);
770 dbri->pipes[n].desc = dbri->pipes[n].first_desc = -1;
772 spin_lock_init(&dbri->cmdlock);
777 dbri->dma->intr[0] = dma_addr;
778 dbri->dbri_irqp = 1;
782 spin_lock(&dbri->cmdlock);
783 cmd = dbri->cmdptr = dbri->dma->cmd;
787 dbri->cmdptr = cmd;
791 sbus_writel(dma_addr, dbri->regs + REG8);
792 spin_unlock(&dbri->cmdlock);
794 spin_unlock_irqrestore(&dbri->lock, flags);
795 dbri_cmdwait(dbri);
812 static inline int pipe_active(struct snd_dbri *dbri, int pipe)
814 return ((pipe >= 0) && (dbri->pipes[pipe].desc != -1));
817 /* reset_pipe(dbri, pipe)
822 static void reset_pipe(struct snd_dbri *dbri, int pipe)
834 sdp = dbri->pipes[pipe].sdp;
841 cmd = dbri_cmdlock(dbri, 3);
845 dbri_cmdsend(dbri, cmd, 3);
847 desc = dbri->pipes[pipe].first_desc;
850 dbri->dma->desc[desc].ba = 0;
851 dbri->dma->desc[desc].nda = 0;
852 desc = dbri->next_desc[desc];
853 } while (desc != -1 && desc != dbri->pipes[pipe].first_desc);
855 dbri->pipes[pipe].desc = -1;
856 dbri->pipes[pipe].first_desc = -1;
862 static void setup_pipe(struct snd_dbri *dbri, int pipe, int sdp)
883 dbri->pipes[pipe].sdp = sdp;
884 dbri->pipes[pipe].desc = -1;
885 dbri->pipes[pipe].first_desc = -1;
887 reset_pipe(dbri, pipe);
893 static void link_time_slot(struct snd_dbri *dbri, int pipe,
908 if (dbri->pipes[pipe].sdp == 0
909 || dbri->pipes[prevpipe].sdp == 0
910 || dbri->pipes[nextpipe].sdp == 0) {
916 dbri->pipes[prevpipe].nextpipe = pipe;
917 dbri->pipes[pipe].nextpipe = nextpipe;
918 dbri->pipes[pipe].length = length;
920 cmd = dbri_cmdlock(dbri, 4);
922 if (dbri->pipes[pipe].sdp & D_SDP_TO_SER) {
929 cycle = dbri->chi_bpf;
945 dbri_cmdsend(dbri, cmd, 4);
952 static void unlink_time_slot(struct snd_dbri *dbri, int pipe,
967 cmd = dbri_cmdlock(dbri, 4);
982 dbri_cmdsend(dbri, cmd, 4);
1002 static void xmit_fixed(struct snd_dbri *dbri, int pipe, unsigned int data)
1012 if (D_SDP_MODE(dbri->pipes[pipe].sdp) == 0) {
1018 if (D_SDP_MODE(dbri->pipes[pipe].sdp) != D_SDP_FIXED) {
1023 if (!(dbri->pipes[pipe].sdp & D_SDP_TO_SER)) {
1031 if (dbri->pipes[pipe].sdp & D_SDP_MSB)
1032 data = reverse_bytes(data, dbri->pipes[pipe].length);
1034 cmd = dbri_cmdlock(dbri, 3);
1040 spin_lock_irqsave(&dbri->lock, flags);
1041 dbri_cmdsend(dbri, cmd, 3);
1042 spin_unlock_irqrestore(&dbri->lock, flags);
1043 dbri_cmdwait(dbri);
1047 static void recv_fixed(struct snd_dbri *dbri, int pipe, volatile __u32 *ptr)
1055 if (D_SDP_MODE(dbri->pipes[pipe].sdp) != D_SDP_FIXED) {
1061 if (dbri->pipes[pipe].sdp & D_SDP_TO_SER) {
1067 dbri->pipes[pipe].recv_fixed_ptr = ptr;
1086 static int setup_descs(struct snd_dbri *dbri, int streamno, unsigned int period)
1088 struct dbri_streaminfo *info = &dbri->stream_info[streamno];
1089 u32 dvma_addr = (u32)dbri->dma_dvma;
1101 if (dbri->pipes[info->pipe].sdp == 0) {
1111 if (!(dbri->pipes[info->pipe].sdp & D_SDP_TO_SER)) {
1117 if (dbri->pipes[info->pipe].sdp & D_SDP_TO_SER) {
1126 if (pipe_active(dbri, info->pipe)) {
1137 desc = dbri->pipes[info->pipe].first_desc;
1140 dbri->dma->desc[desc].ba = 0;
1141 dbri->dma->desc[desc].nda = 0;
1142 desc = dbri->next_desc[desc];
1144 desc != dbri->pipes[info->pipe].first_desc);
1146 dbri->pipes[info->pipe].desc = -1;
1147 dbri->pipes[info->pipe].first_desc = -1;
1154 if (!dbri->dma->desc[desc].ba)
1171 dbri->next_desc[desc] = -1;
1172 dbri->dma->desc[desc].ba = dvma_buffer;
1173 dbri->dma->desc[desc].nda = 0;
1176 dbri->dma->desc[desc].word1 = DBRI_TD_CNT(mylen);
1177 dbri->dma->desc[desc].word4 = 0;
1178 dbri->dma->desc[desc].word1 |= DBRI_TD_F | DBRI_TD_B;
1180 dbri->dma->desc[desc].word1 = 0;
1181 dbri->dma->desc[desc].word4 =
1188 dbri->next_desc[last_desc] = desc;
1189 dbri->dma->desc[last_desc].nda =
1204 dbri->dma->desc[last_desc].nda =
1206 dbri->next_desc[last_desc] = first_desc;
1207 dbri->pipes[info->pipe].first_desc = first_desc;
1208 dbri->pipes[info->pipe].desc = first_desc;
1214 dbri->dma->desc[desc].word1,
1215 dbri->dma->desc[desc].ba,
1216 dbri->dma->desc[desc].nda, dbri->dma->desc[desc].word4);
1217 desc = dbri->next_desc[desc];
1241 static void reset_chi(struct snd_dbri *dbri,
1250 cmd = dbri_cmdlock(dbri, 4);
1257 dbri_cmdsend(dbri, cmd, 4);
1259 dbri->pipes[16].sdp = 1;
1260 dbri->pipes[16].nextpipe = 16;
1262 cmd = dbri_cmdlock(dbri, 4);
1290 dbri->chi_bpf = bits_per_frame;
1304 dbri_cmdsend(dbri, cmd, 4);
1318 static void cs4215_setup_pipes(struct snd_dbri *dbri)
1322 spin_lock_irqsave(&dbri->lock, flags);
1338 setup_pipe(dbri, 4, D_SDP_MEM | D_SDP_TO_SER | D_SDP_MSB);
1339 setup_pipe(dbri, 20, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB);
1340 setup_pipe(dbri, 6, D_SDP_MEM | D_SDP_FROM_SER | D_SDP_MSB);
1341 setup_pipe(dbri, 21, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
1343 setup_pipe(dbri, 17, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB);
1344 setup_pipe(dbri, 18, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
1345 setup_pipe(dbri, 19, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
1346 spin_unlock_irqrestore(&dbri->lock, flags);
1348 dbri_cmdwait(dbri);
1385 static void cs4215_setdata(struct snd_dbri *dbri, int muted)
1388 dbri->mm.data[0] |= 63;
1389 dbri->mm.data[1] |= 63;
1390 dbri->mm.data[2] &= ~15;
1391 dbri->mm.data[3] &= ~15;
1394 struct dbri_streaminfo *info = &dbri->stream_info[DBRI_PLAY];
1398 dbri->mm.data[0] &= ~0x3f; /* Reset the volume bits */
1399 dbri->mm.data[1] &= ~0x3f;
1400 dbri->mm.data[0] |= (DBRI_MAX_VOLUME - left_gain);
1401 dbri->mm.data[1] |= (DBRI_MAX_VOLUME - right_gain);
1404 info = &dbri->stream_info[DBRI_REC];
1407 dbri->mm.data[2] |= CS4215_LG(left_gain);
1408 dbri->mm.data[3] |= CS4215_RG(right_gain);
1411 xmit_fixed(dbri, 20, *(int *)dbri->mm.data);
1417 static void cs4215_open(struct snd_dbri *dbri)
1424 dbri->mm.channels, dbri->mm.precision);
1430 cs4215_setdata(dbri, 1);
1446 spin_lock_irqsave(&dbri->lock, flags);
1447 tmp = sbus_readl(dbri->regs + REG0);
1449 sbus_writel(tmp, dbri->regs + REG0);
1453 (dbri->mm.onboard ? D_PIO0 : D_PIO2), dbri->regs + REG2);
1455 reset_chi(dbri, CHIslave, 128);
1463 data_width = dbri->mm.channels * dbri->mm.precision;
1465 link_time_slot(dbri, 4, 16, 16, data_width, dbri->mm.offset);
1466 link_time_slot(dbri, 20, 4, 16, 32, dbri->mm.offset + 32);
1467 link_time_slot(dbri, 6, 16, 16, data_width, dbri->mm.offset);
1468 link_time_slot(dbri, 21, 6, 16, 16, dbri->mm.offset + 40);
1471 tmp = sbus_readl(dbri->regs + REG0);
1473 sbus_writel(tmp, dbri->regs + REG0);
1474 spin_unlock_irqrestore(&dbri->lock, flags);
1476 cs4215_setdata(dbri, 0);
1482 static int cs4215_setctrl(struct snd_dbri *dbri)
1493 cs4215_setdata(dbri, 1);
1500 val = D_ENPIO | D_PIO1 | (dbri->mm.onboard ? D_PIO0 : D_PIO2);
1501 sbus_writel(val, dbri->regs + REG2);
1523 spin_lock_irqsave(&dbri->lock, flags);
1524 tmp = sbus_readl(dbri->regs + REG0);
1526 sbus_writel(tmp, dbri->regs + REG0);
1528 reset_chi(dbri, CHImaster, 128);
1537 link_time_slot(dbri, 17, 16, 16, 32, dbri->mm.offset);
1538 link_time_slot(dbri, 18, 16, 16, 8, dbri->mm.offset);
1539 link_time_slot(dbri, 19, 18, 16, 8, dbri->mm.offset + 48);
1540 spin_unlock_irqrestore(&dbri->lock, flags);
1543 dbri->mm.ctrl[0] &= ~CS4215_CLB;
1544 xmit_fixed(dbri, 17, *(int *)dbri->mm.ctrl);
1546 spin_lock_irqsave(&dbri->lock, flags);
1547 tmp = sbus_readl(dbri->regs + REG0);
1549 sbus_writel(tmp, dbri->regs + REG0);
1550 spin_unlock_irqrestore(&dbri->lock, flags);
1552 for (i = 10; ((dbri->mm.status & 0xe4) != 0x20); --i)
1557 dbri->mm.status);
1564 recv_fixed(dbri, 19, NULL);
1569 dbri->mm.ctrl[0] |= CS4215_CLB;
1570 xmit_fixed(dbri, 17, *(int *)dbri->mm.ctrl);
1575 cs4215_setdata(dbri, 0);
1586 static int cs4215_prepare(struct snd_dbri *dbri, unsigned int rate,
1604 dbri->mm.ctrl[1] = CS4215_DFR_ULAW;
1605 dbri->mm.precision = 8;
1608 dbri->mm.ctrl[1] = CS4215_DFR_ALAW;
1609 dbri->mm.precision = 8;
1612 dbri->mm.ctrl[1] = CS4215_DFR_LINEAR8;
1613 dbri->mm.precision = 8;
1616 dbri->mm.ctrl[1] = CS4215_DFR_LINEAR16;
1617 dbri->mm.precision = 16;
1625 dbri->mm.ctrl[1] |= CS4215_FREQ[freq_idx].csval;
1626 dbri->mm.ctrl[2] = CS4215_XCLK |
1629 dbri->mm.channels = channels;
1631 dbri->mm.ctrl[1] |= CS4215_DFR_STEREO;
1633 ret = cs4215_setctrl(dbri);
1635 cs4215_open(dbri); /* set codec to data mode */
1643 static int cs4215_init(struct snd_dbri *dbri)
1645 u32 reg2 = sbus_readl(dbri->regs + REG2);
1651 dbri->mm.onboard = 1;
1655 dbri->mm.onboard = 0;
1660 sbus_writel(D_ENPIO2, dbri->regs + REG2);
1669 cs4215_setup_pipes(dbri);
1670 cs4215_init_data(&dbri->mm);
1673 recv_fixed(dbri, 18, &dbri->mm.status);
1674 recv_fixed(dbri, 19, &dbri->mm.version);
1676 dbri->mm.offset = dbri->mm.onboard ? 0 : 8;
1677 if (cs4215_setctrl(dbri) == -1 || dbri->mm.version == 0xff) {
1679 dbri->mm.offset);
1682 dprintk(D_MM, "Found CS4215 at offset %d\n", dbri->mm.offset);
1707 static void xmit_descs(struct snd_dbri *dbri)
1715 if (dbri == NULL)
1718 dvma_addr = (u32)dbri->dma_dvma;
1719 info = &dbri->stream_info[DBRI_REC];
1720 spin_lock_irqsave(&dbri->lock, flags);
1723 first_td = dbri->pipes[info->pipe].first_desc;
1729 cmd = dbri_cmdlock(dbri, 2);
1731 dbri->pipes[info->pipe].sdp
1735 dbri_cmdsend(dbri, cmd, 2);
1738 dbri->pipes[info->pipe].desc = first_td;
1742 info = &dbri->stream_info[DBRI_PLAY];
1745 first_td = dbri->pipes[info->pipe].first_desc;
1751 cmd = dbri_cmdlock(dbri, 2);
1753 dbri->pipes[info->pipe].sdp
1757 dbri_cmdsend(dbri, cmd, 2);
1760 dbri->pipes[info->pipe].desc = first_td;
1764 spin_unlock_irqrestore(&dbri->lock, flags);
1781 static void transmission_complete_intr(struct snd_dbri *dbri, int pipe)
1783 struct dbri_streaminfo *info = &dbri->stream_info[DBRI_PLAY];
1784 int td = dbri->pipes[pipe].desc;
1793 status = DBRI_TD_STATUS(dbri->dma->desc[td].word4);
1799 dbri->dma->desc[td].word4 = 0; /* Reset it for next time. */
1800 info->offset += DBRI_RD_CNT(dbri->dma->desc[td].word1);
1802 td = dbri->next_desc[td];
1803 dbri->pipes[pipe].desc = td;
1807 spin_unlock(&dbri->lock);
1809 spin_lock(&dbri->lock);
1812 static void reception_complete_intr(struct snd_dbri *dbri, int pipe)
1815 int rd = dbri->pipes[pipe].desc;
1823 dbri->pipes[pipe].desc = dbri->next_desc[rd];
1824 status = dbri->dma->desc[rd].word1;
1825 dbri->dma->desc[rd].word1 = 0; /* Reset it for next time. */
1827 info = &dbri->stream_info[DBRI_REC];
1836 spin_unlock(&dbri->lock);
1838 spin_lock(&dbri->lock);
1841 static void dbri_process_one_interrupt(struct snd_dbri *dbri, int x)
1865 reception_complete_intr(dbri, channel);
1869 transmission_complete_intr(dbri, channel);
1881 int td = dbri->pipes[pipe].desc;
1883 dbri->dma->desc[td].word4 = 0;
1884 cmd = dbri_cmdlock(dbri, NoGetLock);
1886 dbri->pipes[pipe].sdp
1888 *(cmd++) = dbri->dma_dvma + dbri_dma_off(desc, td);
1889 dbri_cmdsend(dbri, cmd);
1895 if (dbri->pipes[channel].sdp & D_SDP_MSB)
1896 val = reverse_bytes(val, dbri->pipes[channel].length);
1898 if (dbri->pipes[channel].recv_fixed_ptr)
1899 *(dbri->pipes[channel].recv_fixed_ptr) = val;
1913 static void dbri_process_interrupt_buffer(struct snd_dbri *dbri)
1917 while ((x = dbri->dma->intr[dbri->dbri_irqp]) != 0) {
1918 dbri->dma->intr[dbri->dbri_irqp] = 0;
1919 dbri->dbri_irqp++;
1920 if (dbri->dbri_irqp == DBRI_INT_BLK)
1921 dbri->dbri_irqp = 1;
1923 dbri_process_one_interrupt(dbri, x);
1929 struct snd_dbri *dbri = dev_id;
1933 if (dbri == NULL)
1935 spin_lock(&dbri->lock);
1940 x = sbus_readl(dbri->regs + REG1);
1970 dbri_reset(dbri);
1972 tmp = sbus_readl(dbri->regs + REG0);
1974 sbus_writel(tmp, dbri->regs + REG0);
1978 dbri_process_interrupt_buffer(dbri);
1980 spin_unlock(&dbri->lock);
2046 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2048 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2054 spin_lock_irqsave(&dbri->lock, flags);
2059 spin_unlock_irqrestore(&dbri->lock, flags);
2069 cs4215_open(dbri);
2076 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2077 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2090 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2091 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2096 ret = cs4215_prepare(dbri, params_rate(hw_params),
2111 dma_map_single(&dbri->op->dev,
2125 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2126 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2139 dma_unmap_single(&dbri->op->dev, info->dvma_buffer,
2144 reset_pipe(dbri, info->pipe);
2153 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2154 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2163 spin_lock_irq(&dbri->lock);
2169 ret = setup_descs(dbri, DBRI_STREAMNO(substream),
2172 spin_unlock_irq(&dbri->lock);
2180 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2181 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2189 xmit_descs(dbri);
2193 reset_pipe(dbri, info->pipe);
2204 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2205 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2269 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2272 if (snd_BUG_ON(!dbri))
2274 info = &dbri->stream_info[kcontrol->private_value];
2284 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2286 &dbri->stream_info[kcontrol->private_value];
2312 cs4215_setdata(dbri, 1);
2314 cs4215_setdata(dbri, 0);
2335 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2341 if (snd_BUG_ON(!dbri))
2346 (dbri->mm.data[elem] >> shift) & mask;
2349 (dbri->mm.ctrl[elem - 4] >> shift) & mask;
2360 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2368 if (snd_BUG_ON(!dbri))
2377 dbri->mm.data[elem] = (dbri->mm.data[elem] &
2379 changed = (val != dbri->mm.data[elem]);
2381 dbri->mm.ctrl[elem - 4] = (dbri->mm.ctrl[elem - 4] &
2383 changed = (val != dbri->mm.ctrl[elem - 4]);
2389 dbri->mm.data[elem & 3]);
2395 cs4215_setdata(dbri, 1);
2397 cs4215_setdata(dbri, 0);
2443 struct snd_dbri *dbri;
2447 dbri = card->private_data;
2453 snd_ctl_new1(&dbri_controls[idx], dbri));
2459 dbri->stream_info[idx].left_gain = 0;
2460 dbri->stream_info[idx].right_gain = 0;
2472 struct snd_dbri *dbri = entry->private_data;
2474 snd_iprintf(buffer, "REG0: 0x%x\n", sbus_readl(dbri->regs + REG0));
2475 snd_iprintf(buffer, "REG2: 0x%x\n", sbus_readl(dbri->regs + REG2));
2476 snd_iprintf(buffer, "REG8: 0x%x\n", sbus_readl(dbri->regs + REG8));
2477 snd_iprintf(buffer, "REG9: 0x%x\n", sbus_readl(dbri->regs + REG9));
2484 struct snd_dbri *dbri = entry->private_data;
2489 if (pipe_active(dbri, pipe)) {
2490 struct dbri_pipe *pptr = &dbri->pipes[pipe];
2506 struct snd_dbri *dbri = card->private_data;
2508 snd_card_ro_proc_new(card, "regs", dbri, dbri_regs_read);
2510 snd_card_ro_proc_new(card, "debug", dbri, dbri_debug_read);
2519 static void snd_dbri_free(struct snd_dbri *dbri);
2525 struct snd_dbri *dbri = card->private_data;
2528 spin_lock_init(&dbri->lock);
2529 dbri->op = op;
2530 dbri->irq = irq;
2532 dbri->dma = dma_alloc_coherent(&op->dev, sizeof(struct dbri_dma),
2533 &dbri->dma_dvma, GFP_KERNEL);
2534 if (!dbri->dma)
2538 dbri->dma, dbri->dma_dvma);
2541 dbri->regs_size = resource_size(&op->resource[0]);
2542 dbri->regs = of_ioremap(&op->resource[0], 0,
2543 dbri->regs_size, "DBRI Registers");
2544 if (!dbri->regs) {
2547 (void *)dbri->dma, dbri->dma_dvma);
2551 err = request_irq(dbri->irq, snd_dbri_interrupt, IRQF_SHARED,
2552 "DBRI audio", dbri);
2554 printk(KERN_ERR "DBRI: Can't get irq %d\n", dbri->irq);
2555 of_iounmap(&op->resource[0], dbri->regs, dbri->regs_size);
2557 (void *)dbri->dma, dbri->dma_dvma);
2562 dbri_initialize(dbri);
2563 err = cs4215_init(dbri);
2565 snd_dbri_free(dbri);
2572 static void snd_dbri_free(struct snd_dbri *dbri)
2575 dbri_reset(dbri);
2577 if (dbri->irq)
2578 free_irq(dbri->irq, dbri);
2580 if (dbri->regs)
2581 of_iounmap(&dbri->op->resource[0], dbri->regs, dbri->regs_size);
2583 if (dbri->dma)
2584 dma_free_coherent(&dbri->op->dev,
2586 (void *)dbri->dma, dbri->dma_dvma);
2591 struct snd_dbri *dbri;
2629 dbri = card->private_data;
2647 dev, dbri->regs,
2648 dbri->irq, op->dev.of_node->name[9], dbri->mm.version);
2654 snd_dbri_free(dbri);
2683 .name = "dbri",