Lines Matching refs:val
103 unsigned long val;
105 val = readl_relaxed(base + ZX_I2S_PROCESS_CTRL);
107 val |= ZX_I2S_PROCESS_TX_EN | ZX_I2S_PROCESS_I2S_EN;
109 val &= ~(ZX_I2S_PROCESS_TX_EN | ZX_I2S_PROCESS_I2S_EN);
110 writel_relaxed(val, base + ZX_I2S_PROCESS_CTRL);
115 unsigned long val;
117 val = readl_relaxed(base + ZX_I2S_PROCESS_CTRL);
119 val |= ZX_I2S_PROCESS_RX_EN | ZX_I2S_PROCESS_I2S_EN;
121 val &= ~(ZX_I2S_PROCESS_RX_EN | ZX_I2S_PROCESS_I2S_EN);
122 writel_relaxed(val, base + ZX_I2S_PROCESS_CTRL);
127 unsigned long val;
129 val = readl_relaxed(base + ZX_I2S_FIFO_CTRL);
130 val |= ZX_I2S_FIFO_CTRL_TX_RST | (I2S_DEAGULT_FIFO_THRES << 8);
132 val |= ZX_I2S_FIFO_CTRL_TX_DMA_EN;
134 val &= ~ZX_I2S_FIFO_CTRL_TX_DMA_EN;
135 writel_relaxed(val, base + ZX_I2S_FIFO_CTRL);
140 unsigned long val;
142 val = readl_relaxed(base + ZX_I2S_FIFO_CTRL);
143 val |= ZX_I2S_FIFO_CTRL_RX_RST | (I2S_DEAGULT_FIFO_THRES << 16);
145 val |= ZX_I2S_FIFO_CTRL_RX_DMA_EN;
147 val &= ~ZX_I2S_FIFO_CTRL_RX_DMA_EN;
148 writel_relaxed(val, base + ZX_I2S_FIFO_CTRL);
178 unsigned long val;
180 val = readl_relaxed(i2s->reg_base + ZX_I2S_TIMING_CTRL);
181 val &= ~(ZX_I2S_TIMING_TIMING_MASK | ZX_I2S_TIMING_ALIGN_MASK |
187 val |= (ZX_I2S_TIMING_I2S | ZX_I2S_TIMING_STD_I2S);
190 val |= (ZX_I2S_TIMING_I2S | ZX_I2S_TIMING_MSB_JUSTIF);
193 val |= (ZX_I2S_TIMING_I2S | ZX_I2S_TIMING_LSB_JUSTIF);
204 val |= ZX_I2S_TIMING_SLAVE;
209 val |= ZX_I2S_TIMING_MAST;
216 writel_relaxed(val, i2s->reg_base + ZX_I2S_TIMING_CTRL);
228 unsigned long val;
234 val = readl_relaxed(i2s->reg_base + ZX_I2S_TIMING_CTRL);
235 val &= ~(ZX_I2S_TIMING_TS_WIDTH_MASK | ZX_I2S_TIMING_DATA_SIZE_MASK |
253 val |= ZX_I2S_TIMING_TS_WIDTH(ts_width) | ZX_I2S_TIMING_DATA_SIZE(len);
272 val |= ZX_I2S_TIMING_LANE(lane);
273 val |= ZX_I2S_TIMING_TSCFG(chn_cfg);
274 val |= ZX_I2S_TIMING_CHN(ch_num);
275 writel_relaxed(val, i2s->reg_base + ZX_I2S_TIMING_CTRL);