Lines Matching refs:val
57 u32 val;
60 val = readl(ctx->base + XSPDIF_IRQ_STS_REG);
61 if (val & XSPDIF_CH_STS_MASK) {
62 writel(val & XSPDIF_CH_STS_MASK,
64 val = readl(ctx->base +
66 writel(val & ~XSPDIF_CH_STS_MASK,
80 u32 val;
83 val = readl(ctx->base + XSPDIF_CONTROL_REG);
84 val |= XSPDIF_FIFO_FLUSH_MASK;
85 writel(val, ctx->base + XSPDIF_CONTROL_REG);
109 u32 val, clk_div, clk_cfg;
141 val = readl(ctx->base + XSPDIF_CONTROL_REG);
142 val &= ~XSPDIF_CLOCK_CONFIG_BITS_MASK;
143 val |= clk_cfg << XSPDIF_CLOCK_CONFIG_BITS_SHIFT;
144 writel(val, ctx->base + XSPDIF_CONTROL_REG);
171 u32 val;
175 val = readl(ctx->base + XSPDIF_CONTROL_REG);
180 val |= XSPDIF_CORE_ENABLE_MASK;
181 writel(val, ctx->base + XSPDIF_CONTROL_REG);
188 val &= ~XSPDIF_CORE_ENABLE_MASK;
189 writel(val, ctx->base + XSPDIF_CONTROL_REG);