Lines Matching defs:msp
19 #include <linux/platform_data/asoc-ux500-msp.h>
117 static void set_prot_desc_tx(struct ux500_msp *msp,
127 if (msp->def_elem_len) {
141 writel(temp_reg, msp->registers + MSP_TCF);
144 static void set_prot_desc_rx(struct ux500_msp *msp,
154 if (msp->def_elem_len) {
169 writel(temp_reg, msp->registers + MSP_RCF);
172 static int configure_protocol(struct ux500_msp *msp,
180 msp->def_elem_len = config->def_elem_len;
183 dev_err(msp->dev, "%s: ERROR: Invalid protocol!\n",
194 dev_err(msp->dev,
201 set_prot_desc_tx(msp, protdesc, data_size);
203 set_prot_desc_rx(msp, protdesc, data_size);
206 temp_reg = readl(msp->registers + MSP_GCR) & ~TX_CLK_POL_RISING;
208 writel(temp_reg, msp->registers + MSP_GCR);
209 temp_reg = readl(msp->registers + MSP_GCR) & ~RX_CLK_POL_RISING;
211 writel(temp_reg, msp->registers + MSP_GCR);
216 static int setup_bitclk(struct ux500_msp *msp, struct ux500_msp_config *config)
225 reg_val_GCR = readl(msp->registers + MSP_GCR);
226 writel(reg_val_GCR & ~SRG_ENABLE, msp->registers + MSP_GCR);
249 dev_err(msp->dev, "%s: ERROR: Unknown protocol (%d)!\n",
258 writel(temp_reg, msp->registers + MSP_SRG);
260 msp->f_bitclk = (config->f_inputclk)/(sck_div + 1);
264 reg_val_GCR = readl(msp->registers + MSP_GCR);
265 writel(reg_val_GCR | SRG_ENABLE, msp->registers + MSP_GCR);
271 static int configure_multichannel(struct ux500_msp *msp,
280 dev_err(msp->dev,
294 reg_val_MCR = readl(msp->registers + MSP_MCR);
297 msp->registers + MSP_MCR);
299 msp->registers + MSP_TCE0);
301 msp->registers + MSP_TCE1);
303 msp->registers + MSP_TCE2);
305 msp->registers + MSP_TCE3);
307 dev_err(msp->dev,
315 reg_val_MCR = readl(msp->registers + MSP_MCR);
318 msp->registers + MSP_MCR);
320 msp->registers + MSP_RCE0);
322 msp->registers + MSP_RCE1);
324 msp->registers + MSP_RCE2);
326 msp->registers + MSP_RCE3);
328 dev_err(msp->dev,
334 reg_val_MCR = readl(msp->registers + MSP_MCR);
337 msp->registers + MSP_MCR);
340 msp->registers + MSP_RCM);
342 msp->registers + MSP_RCV);
350 static int enable_msp(struct ux500_msp *msp, struct ux500_msp_config *config)
355 /* Configure msp with protocol dependent settings */
356 configure_protocol(msp, config);
357 setup_bitclk(msp, config);
359 status = configure_multichannel(msp, config);
361 dev_warn(msp->dev,
368 !msp->capture_dma_data.dma_cfg) {
369 dev_err(msp->dev, "%s: ERROR: MSP RX-mode is not configured!",
374 !msp->playback_dma_data.dma_cfg) {
375 dev_err(msp->dev, "%s: ERROR: MSP TX-mode is not configured!",
380 reg_val_DMACR = readl(msp->registers + MSP_DMACR);
385 writel(reg_val_DMACR, msp->registers + MSP_DMACR);
387 writel(config->iodelay, msp->registers + MSP_IODLY);
390 reg_val_GCR = readl(msp->registers + MSP_GCR);
391 writel(reg_val_GCR | FRAME_GEN_ENABLE, msp->registers + MSP_GCR);
396 static void flush_fifo_rx(struct ux500_msp *msp)
401 reg_val_GCR = readl(msp->registers + MSP_GCR);
402 writel(reg_val_GCR | RX_ENABLE, msp->registers + MSP_GCR);
404 reg_val_FLR = readl(msp->registers + MSP_FLR);
406 readl(msp->registers + MSP_DR);
407 reg_val_FLR = readl(msp->registers + MSP_FLR);
410 writel(reg_val_GCR, msp->registers + MSP_GCR);
413 static void flush_fifo_tx(struct ux500_msp *msp)
418 reg_val_GCR = readl(msp->registers + MSP_GCR);
419 writel(reg_val_GCR | TX_ENABLE, msp->registers + MSP_GCR);
420 writel(MSP_ITCR_ITEN | MSP_ITCR_TESTFIFO, msp->registers + MSP_ITCR);
422 reg_val_FLR = readl(msp->registers + MSP_FLR);
424 readl(msp->registers + MSP_TSTDR);
425 reg_val_FLR = readl(msp->registers + MSP_FLR);
427 writel(0x0, msp->registers + MSP_ITCR);
428 writel(reg_val_GCR, msp->registers + MSP_GCR);
431 int ux500_msp_i2s_open(struct ux500_msp *msp,
439 dev_err(msp->dev,
448 dev_err(msp->dev, "%s: Error: No direction selected!\n",
453 tx_busy = (msp->dir_busy & MSP_DIR_TX) > 0;
454 rx_busy = (msp->dir_busy & MSP_DIR_RX) > 0;
456 dev_err(msp->dev, "%s: Error: TX is in use!\n", __func__);
460 dev_err(msp->dev, "%s: Error: RX is in use!\n", __func__);
464 msp->dir_busy |= (tx_sel ? MSP_DIR_TX : 0) | (rx_sel ? MSP_DIR_RX : 0);
479 old_reg = readl(msp->registers + MSP_GCR);
482 writel(new_reg, msp->registers + MSP_GCR);
484 res = enable_msp(msp, config);
486 dev_err(msp->dev, "%s: ERROR: enable_msp failed (%d)!\n",
491 msp->loopback_enable = 1;
494 flush_fifo_tx(msp);
495 flush_fifo_rx(msp);
497 msp->msp_state = MSP_STATE_CONFIGURED;
501 static void disable_msp_rx(struct ux500_msp *msp)
505 reg_val_GCR = readl(msp->registers + MSP_GCR);
506 writel(reg_val_GCR & ~RX_ENABLE, msp->registers + MSP_GCR);
507 reg_val_DMACR = readl(msp->registers + MSP_DMACR);
508 writel(reg_val_DMACR & ~RX_DMA_ENABLE, msp->registers + MSP_DMACR);
509 reg_val_IMSC = readl(msp->registers + MSP_IMSC);
512 msp->registers + MSP_IMSC);
514 msp->dir_busy &= ~MSP_DIR_RX;
517 static void disable_msp_tx(struct ux500_msp *msp)
521 reg_val_GCR = readl(msp->registers + MSP_GCR);
522 writel(reg_val_GCR & ~TX_ENABLE, msp->registers + MSP_GCR);
523 reg_val_DMACR = readl(msp->registers + MSP_DMACR);
524 writel(reg_val_DMACR & ~TX_DMA_ENABLE, msp->registers + MSP_DMACR);
525 reg_val_IMSC = readl(msp->registers + MSP_IMSC);
528 msp->registers + MSP_IMSC);
530 msp->dir_busy &= ~MSP_DIR_TX;
533 static int disable_msp(struct ux500_msp *msp, unsigned int dir)
538 reg_val_GCR = readl(msp->registers + MSP_GCR);
542 reg_val_GCR = readl(msp->registers + MSP_GCR);
544 msp->registers + MSP_GCR);
547 flush_fifo_tx(msp);
550 writel((readl(msp->registers + MSP_GCR) &
551 (~TX_ENABLE)), msp->registers + MSP_GCR);
554 flush_fifo_rx(msp);
557 writel((readl(msp->registers + MSP_GCR) &
559 msp->registers + MSP_GCR);
561 disable_msp_tx(msp);
562 disable_msp_rx(msp);
564 disable_msp_tx(msp);
566 disable_msp_rx(msp);
571 int ux500_msp_i2s_trigger(struct ux500_msp *msp, int cmd, int direction)
575 if (msp->msp_state == MSP_STATE_IDLE) {
576 dev_err(msp->dev, "%s: ERROR: MSP is not configured!\n",
589 reg_val_GCR = readl(msp->registers + MSP_GCR);
590 writel(reg_val_GCR | enable_bit, msp->registers + MSP_GCR);
597 disable_msp_tx(msp);
599 disable_msp_rx(msp);
608 int ux500_msp_i2s_close(struct ux500_msp *msp, unsigned int dir)
612 dev_dbg(msp->dev, "%s: Enter (dir = 0x%01x).\n", __func__, dir);
614 status = disable_msp(msp, dir);
615 if (msp->dir_busy == 0) {
617 msp->msp_state = MSP_STATE_IDLE;
618 writel((readl(msp->registers + MSP_GCR) &
620 msp->registers + MSP_GCR);
622 writel(0, msp->registers + MSP_GCR);
623 writel(0, msp->registers + MSP_TCF);
624 writel(0, msp->registers + MSP_RCF);
625 writel(0, msp->registers + MSP_DMACR);
626 writel(0, msp->registers + MSP_SRG);
627 writel(0, msp->registers + MSP_MCR);
628 writel(0, msp->registers + MSP_RCM);
629 writel(0, msp->registers + MSP_RCV);
630 writel(0, msp->registers + MSP_TCE0);
631 writel(0, msp->registers + MSP_TCE1);
632 writel(0, msp->registers + MSP_TCE2);
633 writel(0, msp->registers + MSP_TCE3);
634 writel(0, msp->registers + MSP_RCE0);
635 writel(0, msp->registers + MSP_RCE1);
636 writel(0, msp->registers + MSP_RCE2);
637 writel(0, msp->registers + MSP_RCE3);
645 struct ux500_msp *msp,
657 msp->playback_dma_data.dma_cfg = devm_kzalloc(&pdev->dev,
660 if (!msp->playback_dma_data.dma_cfg)
663 msp->capture_dma_data.dma_cfg = devm_kzalloc(&pdev->dev,
666 if (!msp->capture_dma_data.dma_cfg)
678 struct ux500_msp *msp;
682 msp = *msp_p;
683 if (!msp)
688 ret = ux500_msp_i2s_of_init_msp(pdev, msp,
695 msp->playback_dma_data.dma_cfg = platform_data->msp_i2s_dma_tx;
696 msp->capture_dma_data.dma_cfg = platform_data->msp_i2s_dma_rx;
697 msp->id = platform_data->id;
700 msp->dev = &pdev->dev;
709 msp->playback_dma_data.tx_rx_addr = res->start + MSP_DR;
710 msp->capture_dma_data.tx_rx_addr = res->start + MSP_DR;
712 msp->registers = devm_ioremap(&pdev->dev, res->start,
714 if (msp->registers == NULL) {
719 msp->msp_state = MSP_STATE_IDLE;
720 msp->loopback_enable = 0;
726 struct ux500_msp *msp)
728 dev_dbg(msp->dev, "%s: Enter (id = %d).\n", __func__, msp->id);