Lines Matching refs:pll_rates
47 unsigned int pll_rates[2];
78 u32 pll_rates[2];
178 if (!(rate % 8000) && priv->pll_rates[J721E_CLK_PARENT_48000])
180 else if (!(rate % 11025) && priv->pll_rates[J721E_CLK_PARENT_44100])
188 if (priv->pll_rates[clk_id] / scki <= J721E_MAX_CLK_HSDIV) {
519 .pll_rates = {
528 .pll_rates = {
537 .pll_rates = {
568 priv->pll_rates[J721E_CLK_PARENT_44100] =
569 match_data->pll_rates[J721E_CLK_PARENT_44100];
571 priv->pll_rates[J721E_CLK_PARENT_44100] = clk_get_rate(pll);
577 priv->pll_rates[J721E_CLK_PARENT_48000] =
578 match_data->pll_rates[J721E_CLK_PARENT_48000];
580 priv->pll_rates[J721E_CLK_PARENT_48000] = clk_get_rate(pll);
584 if (!priv->pll_rates[J721E_CLK_PARENT_44100] &&
585 !priv->pll_rates[J721E_CLK_PARENT_48000]) {
590 if (priv->pll_rates[J721E_CLK_PARENT_44100])
591 pll_rate = priv->pll_rates[J721E_CLK_PARENT_44100];
593 pll_rate = priv->pll_rates[J721E_CLK_PARENT_48000];
598 if (priv->pll_rates[J721E_CLK_PARENT_48000])
599 pll_rate = priv->pll_rates[J721E_CLK_PARENT_48000];
601 pll_rate = priv->pll_rates[J721E_CLK_PARENT_44100];