Lines Matching defs:mcasp
42 #include "davinci-mcasp.h"
73 struct davinci_mcasp *mcasp;
128 static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset,
131 void __iomem *reg = mcasp->base + offset;
135 static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset,
138 void __iomem *reg = mcasp->base + offset;
142 static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset,
145 void __iomem *reg = mcasp->base + offset;
149 static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset,
152 __raw_writel(val, mcasp->base + offset);
155 static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset)
157 return (u32)__raw_readl(mcasp->base + offset);
160 static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val)
164 mcasp_set_bits(mcasp, ctl_reg, val);
169 if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val)
173 if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val))
177 static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp)
179 u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);
180 u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);
185 static inline void mcasp_set_clk_pdir(struct davinci_mcasp *mcasp, bool enable)
189 for_each_set_bit_from(bit, &mcasp->pdir, PIN_BIT_AFSR + 1) {
191 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit));
193 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit));
197 static inline void mcasp_set_axr_pdir(struct davinci_mcasp *mcasp, bool enable)
201 for_each_set_bit(bit, &mcasp->pdir, PIN_BIT_AMUTE) {
203 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit));
205 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit));
209 static void mcasp_start_rx(struct davinci_mcasp *mcasp)
211 if (mcasp->rxnumevt) { /* enable FIFO */
212 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
214 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
215 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
219 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
220 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
226 if (mcasp_is_synchronous(mcasp)) {
227 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
228 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
229 mcasp_set_clk_pdir(mcasp, true);
233 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
234 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
236 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
238 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
239 if (mcasp_is_synchronous(mcasp))
240 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
243 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
244 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);
247 static void mcasp_start_tx(struct davinci_mcasp *mcasp)
251 if (mcasp->txnumevt) { /* enable FIFO */
252 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
254 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
255 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
259 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
260 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
261 mcasp_set_clk_pdir(mcasp, true);
264 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
265 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
269 while ((mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG) & XRDATA) &&
273 mcasp_set_axr_pdir(mcasp, true);
276 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
278 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
281 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,
282 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);
285 static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream)
287 mcasp->streams++;
290 mcasp_start_tx(mcasp);
292 mcasp_start_rx(mcasp);
295 static void mcasp_stop_rx(struct davinci_mcasp *mcasp)
298 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
299 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);
305 if (mcasp_is_synchronous(mcasp) && !mcasp->streams) {
306 mcasp_set_clk_pdir(mcasp, false);
307 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0);
310 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0);
311 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
313 if (mcasp->rxnumevt) { /* disable FIFO */
314 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
316 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
320 static void mcasp_stop_tx(struct davinci_mcasp *mcasp)
325 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,
326 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);
332 if (mcasp_is_synchronous(mcasp) && mcasp->streams)
335 mcasp_set_clk_pdir(mcasp, false);
338 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val);
339 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
341 if (mcasp->txnumevt) { /* disable FIFO */
342 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
344 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
347 mcasp_set_axr_pdir(mcasp, false);
350 static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream)
352 mcasp->streams--;
355 mcasp_stop_tx(mcasp);
357 mcasp_stop_rx(mcasp);
362 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
364 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK];
368 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG);
370 dev_warn(mcasp->dev, "Transmit buffer underflow\n");
373 substream = mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK];
379 dev_warn(mcasp->dev, "unhandled tx event. txstat: 0x%08x\n",
386 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, handled_mask);
393 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
395 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE];
399 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG);
401 dev_warn(mcasp->dev, "Receive buffer overflow\n");
404 substream = mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE];
410 dev_warn(mcasp->dev, "unhandled rx event. rxstat: 0x%08x\n",
417 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, handled_mask);
424 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
427 if (mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK])
430 if (mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE])
439 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
448 pm_runtime_get_sync(mcasp->dev);
451 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
452 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
458 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
459 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
465 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
466 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
475 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
476 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
485 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(data_delay),
487 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(data_delay),
493 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
494 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
496 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
497 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
500 set_bit(PIN_BIT_ACLKX, &mcasp->pdir);
501 set_bit(PIN_BIT_ACLKR, &mcasp->pdir);
503 set_bit(PIN_BIT_AFSX, &mcasp->pdir);
504 set_bit(PIN_BIT_AFSR, &mcasp->pdir);
506 mcasp->bclk_master = 1;
510 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
511 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
513 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
514 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
517 set_bit(PIN_BIT_ACLKX, &mcasp->pdir);
518 set_bit(PIN_BIT_ACLKR, &mcasp->pdir);
520 clear_bit(PIN_BIT_AFSX, &mcasp->pdir);
521 clear_bit(PIN_BIT_AFSR, &mcasp->pdir);
523 mcasp->bclk_master = 1;
527 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
528 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
530 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
531 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
534 clear_bit(PIN_BIT_ACLKX, &mcasp->pdir);
535 clear_bit(PIN_BIT_ACLKR, &mcasp->pdir);
537 set_bit(PIN_BIT_AFSX, &mcasp->pdir);
538 set_bit(PIN_BIT_AFSR, &mcasp->pdir);
540 mcasp->bclk_master = 0;
544 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
545 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
547 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
548 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
551 clear_bit(PIN_BIT_ACLKX, &mcasp->pdir);
552 clear_bit(PIN_BIT_ACLKR, &mcasp->pdir);
554 clear_bit(PIN_BIT_AFSX, &mcasp->pdir);
555 clear_bit(PIN_BIT_AFSR, &mcasp->pdir);
557 mcasp->bclk_master = 0;
566 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
567 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
571 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
572 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
576 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
577 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
581 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
582 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
594 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
595 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
597 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
598 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
601 mcasp->dai_fmt = fmt;
603 pm_runtime_put(mcasp->dev);
607 static int __davinci_mcasp_set_clkdiv(struct davinci_mcasp *mcasp, int div_id,
610 pm_runtime_get_sync(mcasp->dev);
613 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
615 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
620 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG,
622 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG,
625 mcasp->bclk_div = div;
639 mcasp->slot_width = div / mcasp->tdm_slots;
640 if (div % mcasp->tdm_slots)
641 dev_warn(mcasp->dev,
643 __func__, div, mcasp->tdm_slots);
650 pm_runtime_put(mcasp->dev);
657 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
659 return __davinci_mcasp_set_clkdiv(mcasp, div_id, div, 1);
665 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
667 pm_runtime_get_sync(mcasp->dev);
672 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
674 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
676 clear_bit(PIN_BIT_AHCLKX, &mcasp->pdir);
679 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
681 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
683 set_bit(PIN_BIT_AHCLKX, &mcasp->pdir);
686 dev_err(mcasp->dev, "Invalid clk id: %d\n", clk_id);
691 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
692 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
693 set_bit(PIN_BIT_AHCLKX, &mcasp->pdir);
699 mcasp->sysclk_freq = freq;
701 pm_runtime_put(mcasp->dev);
706 static int davinci_mcasp_ch_constraint(struct davinci_mcasp *mcasp, int stream,
709 struct snd_pcm_hw_constraint_list *cl = &mcasp->chconstr[stream];
711 int slots = mcasp->tdm_slots;
714 if (mcasp->tdm_mask[stream])
715 slots = hweight32(mcasp->tdm_mask[stream]);
728 static int davinci_mcasp_set_ch_constraints(struct davinci_mcasp *mcasp)
732 for (i = 0; i < mcasp->num_serializer; i++)
733 if (mcasp->serial_dir[i] == TX_MODE)
735 else if (mcasp->serial_dir[i] == RX_MODE)
738 ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_PLAYBACK,
743 ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_CAPTURE,
755 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
757 dev_dbg(mcasp->dev,
762 dev_err(mcasp->dev,
770 dev_err(mcasp->dev, "%s: Unsupported slot_width %d\n",
775 mcasp->tdm_slots = slots;
776 mcasp->tdm_mask[SNDRV_PCM_STREAM_PLAYBACK] = tx_mask;
777 mcasp->tdm_mask[SNDRV_PCM_STREAM_CAPTURE] = rx_mask;
778 mcasp->slot_width = slot_width;
780 return davinci_mcasp_set_ch_constraints(mcasp);
783 static int davinci_config_channel_size(struct davinci_mcasp *mcasp,
790 if (mcasp->slot_width)
791 slot_width = mcasp->slot_width;
792 else if (mcasp->max_format_width)
793 slot_width = mcasp->max_format_width;
805 if ((mcasp->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) ==
817 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
818 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt),
820 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt),
822 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate),
824 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate),
826 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask);
829 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask);
834 static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream,
837 struct snd_dmaengine_dai_dma_data *dma_data = &mcasp->dma_data[stream];
841 u8 slots = mcasp->tdm_slots;
847 if (mcasp->version < MCASP_VERSION_3)
848 mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
851 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
852 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
855 mcasp->active_serializers[SNDRV_PCM_STREAM_CAPTURE];
857 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
858 mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS);
860 mcasp->active_serializers[SNDRV_PCM_STREAM_PLAYBACK];
864 for (i = 0; i < mcasp->num_serializer; i++) {
865 mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
866 mcasp->serial_dir[i]);
867 if (mcasp->serial_dir[i] == TX_MODE &&
869 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
870 mcasp->dismod, DISMOD_MASK);
871 set_bit(PIN_BIT_AXR(i), &mcasp->pdir);
873 } else if (mcasp->serial_dir[i] == RX_MODE &&
875 clear_bit(PIN_BIT_AXR(i), &mcasp->pdir);
879 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
882 if (mcasp->serial_dir[i] != INACTIVE_MODE)
883 mcasp_mod_bits(mcasp,
885 mcasp->dismod, DISMOD_MASK);
886 clear_bit(PIN_BIT_AXR(i), &mcasp->pdir);
892 numevt = mcasp->txnumevt;
893 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
896 numevt = mcasp->rxnumevt;
897 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
901 dev_warn(mcasp->dev, "stream has more channels (%d) than are "
902 "enabled in mcasp (%d)\n", channels,
926 dev_err(mcasp->dev, "Invalid combination of period words and "
944 mcasp_mod_bits(mcasp, reg, active_serializers, NUMDMA_MASK);
945 mcasp_mod_bits(mcasp, reg, NUMEVT(numevt), NUMEVT_MASK);
953 mcasp->active_serializers[stream] = active_serializers;
958 static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream,
967 total_slots = mcasp->tdm_slots;
975 if (mcasp->tdm_mask[stream]) {
976 active_slots = hweight32(mcasp->tdm_mask[stream]);
982 if ((1 << i) & mcasp->tdm_mask[stream]) {
999 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
1001 if (!mcasp->dat_port)
1005 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask);
1006 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD);
1007 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
1010 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask);
1011 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD);
1012 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG,
1019 if (mcasp_is_synchronous(mcasp) && !mcasp->channels)
1020 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
1028 static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp,
1036 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(6) | TXSSZ(15));
1039 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180));
1042 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
1045 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC);
1047 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
1050 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
1053 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN);
1092 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRA_REG, cs_value);
1093 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRB_REG, cs_value);
1098 static int davinci_mcasp_calc_clk_div(struct davinci_mcasp *mcasp,
1102 u32 reg = mcasp_get_reg(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG);
1118 dev_warn(mcasp->dev, "Too fast reference clock (%u)\n",
1136 dev_info(mcasp->dev, "Sample-rate is off by %d PPM\n",
1139 __davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_BCLK, div, 0);
1141 __davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_AUXCLK,
1148 static inline u32 davinci_mcasp_tx_delay(struct davinci_mcasp *mcasp)
1150 if (!mcasp->txnumevt)
1153 return mcasp_get_reg(mcasp, mcasp->fifo_base + MCASP_WFIFOSTS_OFFSET);
1156 static inline u32 davinci_mcasp_rx_delay(struct davinci_mcasp *mcasp)
1158 if (!mcasp->rxnumevt)
1161 return mcasp_get_reg(mcasp, mcasp->fifo_base + MCASP_RFIFOSTS_OFFSET);
1168 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1172 fifo_use = davinci_mcasp_tx_delay(mcasp);
1174 fifo_use = davinci_mcasp_rx_delay(mcasp);
1188 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1221 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
1225 ret = davinci_mcasp_set_dai_fmt(cpu_dai, mcasp->dai_fmt);
1230 * If mcasp is BCLK master, and a BCLK divider was not provided by
1233 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
1234 int slots = mcasp->tdm_slots;
1238 if (mcasp->slot_width)
1239 sbits = mcasp->slot_width;
1241 davinci_mcasp_calc_clk_div(mcasp, mcasp->sysclk_freq,
1245 ret = mcasp_common_hw_param(mcasp, substream->stream,
1250 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1251 ret = mcasp_dit_hw_param(mcasp, params_rate(params));
1253 ret = mcasp_i2s_hw_param(mcasp, substream->stream,
1259 davinci_config_channel_size(mcasp, word_length);
1261 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) {
1262 mcasp->channels = channels;
1263 if (!mcasp->max_format_width)
1264 mcasp->max_format_width = word_length;
1273 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1280 davinci_mcasp_start(mcasp, substream->stream);
1285 davinci_mcasp_stop(mcasp, substream->stream);
1304 slot_width = rd->mcasp->slot_width;
1326 format_width = rd->mcasp->max_format_width;
1353 int slots = rd->mcasp->tdm_slots;
1357 if (rd->mcasp->slot_width)
1358 sbits = rd->mcasp->slot_width;
1370 if (rd->mcasp->auxclk_fs_ratio)
1372 rd->mcasp->auxclk_fs_ratio;
1374 sysclk_freq = rd->mcasp->sysclk_freq;
1376 ppm = davinci_mcasp_calc_clk_div(rd->mcasp, sysclk_freq,
1388 dev_dbg(rd->mcasp->dev,
1403 int slots = rd->mcasp->tdm_slots;
1414 if (rd->mcasp->auxclk_fs_ratio)
1416 rd->mcasp->auxclk_fs_ratio;
1418 sysclk_freq = rd->mcasp->sysclk_freq;
1420 if (rd->mcasp->slot_width)
1421 sbits = rd->mcasp->slot_width;
1423 ppm = davinci_mcasp_calc_clk_div(rd->mcasp, sysclk_freq,
1432 dev_dbg(rd->mcasp->dev,
1456 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1458 &mcasp->ruledata[substream->stream];
1461 int tdm_slots = mcasp->tdm_slots;
1464 if (mcasp->substreams[substream->stream])
1467 mcasp->substreams[substream->stream] = substream;
1469 if (mcasp->tdm_mask[substream->stream])
1470 tdm_slots = hweight32(mcasp->tdm_mask[substream->stream]);
1472 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1484 for (i = 0; i < mcasp->num_serializer; i++) {
1485 if (mcasp->serial_dir[i] == dir)
1489 ruledata->mcasp = mcasp;
1498 if (mcasp->channels && mcasp->channels < max_channels &&
1500 max_channels = mcasp->channels;
1514 &mcasp->chconstr[substream->stream]);
1516 if (mcasp->max_format_width) {
1529 else if (mcasp->slot_width) {
1544 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
1572 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1574 mcasp->substreams[substream->stream] = NULL;
1575 mcasp->active_serializers[substream->stream] = 0;
1577 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1581 mcasp->channels = 0;
1582 mcasp->max_format_width = 0;
1600 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
1602 dai->playback_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
1603 dai->capture_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
1623 .name = "davinci-mcasp.0",
1644 .name = "davinci-mcasp.1",
1659 .name = "davinci-mcasp",
1690 .compatible = "ti,dm646x-mcasp-audio",
1694 .compatible = "ti,da830-mcasp-audio",
1698 .compatible = "ti,am33xx-mcasp-audio",
1702 .compatible = "ti,dra7-mcasp-audio",
1884 static int davinci_mcasp_get_dma_type(struct davinci_mcasp *mcasp)
1890 if (!mcasp->dev->of_node)
1893 tmp = mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK].filter_data;
1894 chan = dma_request_chan(mcasp->dev, tmp);
1897 dev_err(mcasp->dev,
1911 dev_dbg(mcasp->dev, "DMA controller has no of-node\n");
1917 dev_dbg(mcasp->dev, "DMA controller compatible = \"%s\"\n", tmp);
1975 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
1977 if (mcasp->num_serializer && offset < mcasp->num_serializer &&
1978 mcasp->serial_dir[offset] != INACTIVE_MODE) {
1979 dev_err(mcasp->dev, "AXR%u pin is used for audio\n", offset);
1985 return pm_runtime_get_sync(mcasp->dev);
1990 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
1993 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset));
1996 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset));
1998 pm_runtime_put_sync(mcasp->dev);
2004 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
2008 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset));
2010 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset));
2012 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PFUNC_REG);
2015 mcasp_set_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset));
2018 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset));
2027 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
2030 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset));
2032 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset));
2038 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
2041 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PFUNC_REG);
2044 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset));
2047 mcasp_set_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset));
2055 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
2058 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDSET_REG);
2068 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
2071 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDIR_REG);
2091 static int davinci_mcasp_init_gpiochip(struct davinci_mcasp *mcasp)
2093 if (!of_property_read_bool(mcasp->dev->of_node, "gpio-controller"))
2096 mcasp->gpio_chip = davinci_mcasp_template_chip;
2097 mcasp->gpio_chip.label = dev_name(mcasp->dev);
2098 mcasp->gpio_chip.parent = mcasp->dev;
2100 mcasp->gpio_chip.of_node = mcasp->dev->of_node;
2103 return devm_gpiochip_add_data(mcasp->dev, &mcasp->gpio_chip, mcasp);
2107 static inline int davinci_mcasp_init_gpiochip(struct davinci_mcasp *mcasp)
2113 static int davinci_mcasp_get_dt_params(struct davinci_mcasp *mcasp)
2115 struct device_node *np = mcasp->dev->of_node;
2124 mcasp->auxclk_fs_ratio = val;
2134 struct davinci_mcasp *mcasp;
2145 mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp),
2147 if (!mcasp)
2167 mcasp->base = devm_ioremap_resource(&pdev->dev, mem);
2168 if (IS_ERR(mcasp->base))
2169 return PTR_ERR(mcasp->base);
2173 mcasp->op_mode = pdata->op_mode;
2175 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) {
2179 mcasp->tdm_slots = 2;
2183 mcasp->tdm_slots = 32;
2185 mcasp->tdm_slots = pdata->tdm_slots;
2189 mcasp->num_serializer = pdata->num_serializer;
2191 mcasp->context.xrsr_regs = devm_kcalloc(&pdev->dev,
2192 mcasp->num_serializer, sizeof(u32),
2194 if (!mcasp->context.xrsr_regs) {
2199 mcasp->serial_dir = pdata->serial_dir;
2200 mcasp->version = pdata->version;
2201 mcasp->txnumevt = pdata->txnumevt;
2202 mcasp->rxnumevt = pdata->rxnumevt;
2203 mcasp->dismod = pdata->dismod;
2205 mcasp->dev = &pdev->dev;
2218 irq_name, mcasp);
2224 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN;
2225 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN;
2238 IRQF_ONESHOT, irq_name, mcasp);
2244 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN;
2257 IRQF_ONESHOT, irq_name, mcasp);
2263 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN;
2268 mcasp->dat_port = true;
2270 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
2276 dma = &mcasp->dma_request[SNDRV_PCM_STREAM_PLAYBACK];
2290 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
2291 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
2298 dma = &mcasp->dma_request[SNDRV_PCM_STREAM_CAPTURE];
2312 if (mcasp->version < MCASP_VERSION_3) {
2313 mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE;
2315 mcasp->dat_port = true;
2317 mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE;
2327 mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list =
2328 devm_kcalloc(mcasp->dev,
2329 32 + mcasp->num_serializer - 1,
2333 mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list =
2334 devm_kcalloc(mcasp->dev,
2335 32 + mcasp->num_serializer - 1,
2339 if (!mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list ||
2340 !mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list) {
2345 ret = davinci_mcasp_set_ch_constraints(mcasp);
2349 dev_set_drvdata(&pdev->dev, mcasp);
2354 pm_runtime_get_sync(mcasp->dev);
2355 mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000);
2356 pm_runtime_put(mcasp->dev);
2358 ret = davinci_mcasp_init_gpiochip(mcasp);
2362 ret = davinci_mcasp_get_dt_params(mcasp);
2373 ret = davinci_mcasp_get_dma_type(mcasp);
2413 struct davinci_mcasp *mcasp = dev_get_drvdata(dev);
2414 struct davinci_mcasp_context *context = &mcasp->context;
2419 context->config_regs[i] = mcasp_get_reg(mcasp, context_regs[i]);
2421 if (mcasp->txnumevt) {
2422 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
2423 context->afifo_regs[0] = mcasp_get_reg(mcasp, reg);
2425 if (mcasp->rxnumevt) {
2426 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
2427 context->afifo_regs[1] = mcasp_get_reg(mcasp, reg);
2430 for (i = 0; i < mcasp->num_serializer; i++)
2431 context->xrsr_regs[i] = mcasp_get_reg(mcasp,
2439 struct davinci_mcasp *mcasp = dev_get_drvdata(dev);
2440 struct davinci_mcasp_context *context = &mcasp->context;
2445 mcasp_set_reg(mcasp, context_regs[i], context->config_regs[i]);
2447 if (mcasp->txnumevt) {
2448 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
2449 mcasp_set_reg(mcasp, reg, context->afifo_regs[0]);
2451 if (mcasp->rxnumevt) {
2452 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
2453 mcasp_set_reg(mcasp, reg, context->afifo_regs[1]);
2456 for (i = 0; i < mcasp->num_serializer; i++)
2457 mcasp_set_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
2475 .name = "davinci-mcasp",