Lines Matching defs:data
18 int tegra_asoc_utils_set_rate(struct tegra_asoc_utils_data *data, int srate,
30 if (data->soc == TEGRA_ASOC_UTILS_SOC_TEGRA20)
32 else if (data->soc == TEGRA_ASOC_UTILS_SOC_TEGRA30)
43 if (data->soc == TEGRA_ASOC_UTILS_SOC_TEGRA20)
45 else if (data->soc == TEGRA_ASOC_UTILS_SOC_TEGRA30)
54 clk_change = ((new_baseclock != data->set_baseclock) ||
55 (mclk != data->set_mclk));
59 data->set_baseclock = 0;
60 data->set_mclk = 0;
62 clk_disable_unprepare(data->clk_cdev1);
64 err = clk_set_rate(data->clk_pll_a, new_baseclock);
66 dev_err(data->dev, "Can't set pll_a rate: %d\n", err);
70 err = clk_set_rate(data->clk_pll_a_out0, mclk);
72 dev_err(data->dev, "Can't set pll_a_out0 rate: %d\n", err);
78 err = clk_prepare_enable(data->clk_cdev1);
80 dev_err(data->dev, "Can't enable cdev1: %d\n", err);
84 data->set_baseclock = new_baseclock;
85 data->set_mclk = mclk;
91 int tegra_asoc_utils_set_ac97_rate(struct tegra_asoc_utils_data *data)
97 clk_disable_unprepare(data->clk_cdev1);
103 err = clk_set_rate(data->clk_pll_a, pll_rate);
105 dev_err(data->dev, "Can't set pll_a rate: %d\n", err);
109 err = clk_set_rate(data->clk_pll_a_out0, ac97_rate);
111 dev_err(data->dev, "Can't set pll_a_out0 rate: %d\n", err);
117 err = clk_prepare_enable(data->clk_cdev1);
119 dev_err(data->dev, "Can't enable cdev1: %d\n", err);
123 data->set_baseclock = pll_rate;
124 data->set_mclk = ac97_rate;
130 int tegra_asoc_utils_init(struct tegra_asoc_utils_data *data,
136 data->dev = dev;
139 data->soc = TEGRA_ASOC_UTILS_SOC_TEGRA20;
141 data->soc = TEGRA_ASOC_UTILS_SOC_TEGRA30;
143 data->soc = TEGRA_ASOC_UTILS_SOC_TEGRA114;
145 data->soc = TEGRA_ASOC_UTILS_SOC_TEGRA124;
147 dev_err(data->dev, "SoC unknown to Tegra ASoC utils\n");
151 data->clk_pll_a = devm_clk_get(dev, "pll_a");
152 if (IS_ERR(data->clk_pll_a)) {
153 dev_err(data->dev, "Can't retrieve clk pll_a\n");
154 return PTR_ERR(data->clk_pll_a);
157 data->clk_pll_a_out0 = devm_clk_get(dev, "pll_a_out0");
158 if (IS_ERR(data->clk_pll_a_out0)) {
159 dev_err(data->dev, "Can't retrieve clk pll_a_out0\n");
160 return PTR_ERR(data->clk_pll_a_out0);
163 data->clk_cdev1 = devm_clk_get(dev, "mclk");
164 if (IS_ERR(data->clk_cdev1)) {
165 dev_err(data->dev, "Can't retrieve clk cdev1\n");
166 return PTR_ERR(data->clk_cdev1);
174 data->soc > TEGRA_ASOC_UTILS_SOC_TEGRA20) {
175 dev_warn(data->dev,
177 dev_warn(data->dev,
181 dev_err(data->dev, "Can't retrieve clk extern1\n");
185 ret = clk_set_parent(clk_extern1, data->clk_pll_a_out0);
187 dev_err(data->dev,
194 dev_err(data->dev, "Can't retrieve pmc_clk_out_1\n");
200 dev_err(data->dev,
205 data->clk_cdev1 = clk_out_1;
213 ret = clk_prepare_enable(data->clk_cdev1);
215 dev_err(data->dev, "Can't enable cdev1: %d\n", ret);