Lines Matching refs:val
69 unsigned int mask = 0, val = 0;
81 val |= TEGRA30_I2S_CTRL_MASTER_ENABLE;
93 val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC;
94 val |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
97 val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC;
98 val |= TEGRA30_I2S_CTRL_LRCK_R_LOW;
101 val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK;
102 val |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
105 val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK;
106 val |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
109 val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK;
110 val |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
117 regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL, mask, val);
129 unsigned int mask, val, reg;
139 val = TEGRA30_I2S_CTRL_BIT_SIZE_16;
146 regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL, mask, val);
163 val = bitcnt << TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT;
166 val |= TEGRA30_I2S_TIMING_NON_SYM_ENABLE;
168 regmap_write(i2s->regmap, TEGRA30_I2S_TIMING, val);
191 val = (1 << TEGRA30_I2S_OFFSET_RX_DATA_OFFSET_SHIFT) |
193 regmap_write(i2s->regmap, TEGRA30_I2S_OFFSET, val);
262 unsigned int mask, val;
271 val = (tx_mask << TEGRA30_I2S_SLOT_CTRL_TX_SLOT_ENABLES_SHIFT) |
276 regmap_update_bits(i2s->regmap, TEGRA30_I2S_SLOT_CTRL, mask, val);