Lines Matching refs:ret
52 int ret;
54 ret = clk_prepare_enable(i2s->clk_i2s);
55 if (ret) {
56 dev_err(dev, "clk_enable failed: %d\n", ret);
57 return ret;
130 int ret, sample_size, srate, i2sclock, bitcnt;
157 ret = clk_set_rate(i2s->clk_i2s, i2sclock);
158 if (ret) {
159 dev_err(dev, "Can't set I2S clock rate: %d\n", ret);
160 return ret;
401 int ret;
405 ret = -ENOMEM;
413 ret = -ENODEV;
421 ret = of_property_read_u32_array(pdev->dev.of_node,
424 if (ret < 0)
433 ret = PTR_ERR(i2s->clk_i2s);
439 ret = PTR_ERR(regs);
447 ret = PTR_ERR(i2s->regmap);
454 ret = tegra30_i2s_runtime_resume(&pdev->dev);
455 if (ret)
461 ret = tegra30_ahub_allocate_tx_fifo(&i2s->playback_fifo_cif,
465 if (ret) {
466 dev_err(&pdev->dev, "Could not alloc TX FIFO: %d\n", ret);
469 ret = tegra30_ahub_set_rx_cif_source(i2s->playback_i2s_cif,
471 if (ret) {
472 dev_err(&pdev->dev, "Could not route TX FIFO: %d\n", ret);
478 ret = tegra30_ahub_allocate_rx_fifo(&i2s->capture_fifo_cif,
482 if (ret) {
483 dev_err(&pdev->dev, "Could not alloc RX FIFO: %d\n", ret);
486 ret = tegra30_ahub_set_rx_cif_source(i2s->capture_fifo_cif,
488 if (ret) {
489 dev_err(&pdev->dev, "Could not route TX FIFO: %d\n", ret);
493 ret = snd_soc_register_component(&pdev->dev, &tegra30_i2s_component,
495 if (ret) {
496 dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
497 ret = -ENOMEM;
501 ret = tegra_pcm_platform_register_with_chan_names(&pdev->dev,
504 if (ret) {
505 dev_err(&pdev->dev, "Could not register PCM: %d\n", ret);
529 return ret;
567 int ret;
569 ret = pm_runtime_get_sync(dev);
570 if (ret < 0) {
572 return ret;
574 ret = regcache_sync(i2s->regmap);
577 return ret;