Lines Matching defs:i2s
36 #define DRV_NAME "tegra30-i2s"
40 struct tegra30_i2s *i2s = dev_get_drvdata(dev);
42 regcache_cache_only(i2s->regmap, true);
44 clk_disable_unprepare(i2s->clk_i2s);
51 struct tegra30_i2s *i2s = dev_get_drvdata(dev);
54 ret = clk_prepare_enable(i2s->clk_i2s);
60 regcache_cache_only(i2s->regmap, false);
68 struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
117 regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL, mask, val);
128 struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
146 regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL, mask, val);
157 ret = clk_set_rate(i2s->clk_i2s, i2sclock);
168 regmap_write(i2s->regmap, TEGRA30_I2S_TIMING, val);
189 i2s->soc_data->set_audio_cif(i2s->regmap, reg, &cif_conf);
193 regmap_write(i2s->regmap, TEGRA30_I2S_OFFSET, val);
198 static void tegra30_i2s_start_playback(struct tegra30_i2s *i2s)
200 tegra30_ahub_enable_tx_fifo(i2s->playback_fifo_cif);
201 regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL,
206 static void tegra30_i2s_stop_playback(struct tegra30_i2s *i2s)
208 tegra30_ahub_disable_tx_fifo(i2s->playback_fifo_cif);
209 regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL,
213 static void tegra30_i2s_start_capture(struct tegra30_i2s *i2s)
215 tegra30_ahub_enable_rx_fifo(i2s->capture_fifo_cif);
216 regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL,
221 static void tegra30_i2s_stop_capture(struct tegra30_i2s *i2s)
223 regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL,
225 tegra30_ahub_disable_rx_fifo(i2s->capture_fifo_cif);
231 struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
238 tegra30_i2s_start_playback(i2s);
240 tegra30_i2s_start_capture(i2s);
246 tegra30_i2s_stop_playback(i2s);
248 tegra30_i2s_stop_capture(i2s);
261 struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
276 regmap_update_bits(i2s->regmap, TEGRA30_I2S_SLOT_CTRL, mask, val);
278 regmap_update_bits(i2s->regmap, TEGRA30_I2S_CH_CTRL,
287 struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
289 dai->capture_dma_data = &i2s->capture_dma_data;
290 dai->playback_dma_data = &i2s->playback_dma_data;
390 { .compatible = "nvidia,tegra124-i2s", .data = &tegra124_i2s_config },
391 { .compatible = "nvidia,tegra30-i2s", .data = &tegra30_i2s_config },
397 struct tegra30_i2s *i2s;
403 i2s = devm_kzalloc(&pdev->dev, sizeof(struct tegra30_i2s), GFP_KERNEL);
404 if (!i2s) {
408 dev_set_drvdata(&pdev->dev, i2s);
416 i2s->soc_data = (struct tegra30_i2s_soc_data *)match->data;
418 i2s->dai = tegra30_i2s_dai_template;
419 i2s->dai.name = dev_name(&pdev->dev);
427 i2s->playback_i2s_cif = cif_ids[0];
428 i2s->capture_i2s_cif = cif_ids[1];
430 i2s->clk_i2s = clk_get(&pdev->dev, NULL);
431 if (IS_ERR(i2s->clk_i2s)) {
432 dev_err(&pdev->dev, "Can't retrieve i2s clock\n");
433 ret = PTR_ERR(i2s->clk_i2s);
443 i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
445 if (IS_ERR(i2s->regmap)) {
447 ret = PTR_ERR(i2s->regmap);
450 regcache_cache_only(i2s->regmap, true);
459 i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
460 i2s->playback_dma_data.maxburst = 4;
461 ret = tegra30_ahub_allocate_tx_fifo(&i2s->playback_fifo_cif,
462 i2s->playback_dma_chan,
463 sizeof(i2s->playback_dma_chan),
464 &i2s->playback_dma_data.addr);
469 ret = tegra30_ahub_set_rx_cif_source(i2s->playback_i2s_cif,
470 i2s->playback_fifo_cif);
476 i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
477 i2s->capture_dma_data.maxburst = 4;
478 ret = tegra30_ahub_allocate_rx_fifo(&i2s->capture_fifo_cif,
479 i2s->capture_dma_chan,
480 sizeof(i2s->capture_dma_chan),
481 &i2s->capture_dma_data.addr);
486 ret = tegra30_ahub_set_rx_cif_source(i2s->capture_fifo_cif,
487 i2s->capture_i2s_cif);
494 &i2s->dai, 1);
502 &i2s->dma_config, i2s->playback_dma_chan,
503 i2s->capture_dma_chan);
514 tegra30_ahub_unset_rx_cif_source(i2s->capture_fifo_cif);
516 tegra30_ahub_free_rx_fifo(i2s->capture_fifo_cif);
518 tegra30_ahub_unset_rx_cif_source(i2s->playback_i2s_cif);
520 tegra30_ahub_free_tx_fifo(i2s->playback_fifo_cif);
527 clk_put(i2s->clk_i2s);
534 struct tegra30_i2s *i2s = dev_get_drvdata(&pdev->dev);
543 tegra30_ahub_unset_rx_cif_source(i2s->capture_fifo_cif);
544 tegra30_ahub_free_rx_fifo(i2s->capture_fifo_cif);
546 tegra30_ahub_unset_rx_cif_source(i2s->playback_i2s_cif);
547 tegra30_ahub_free_tx_fifo(i2s->playback_fifo_cif);
549 clk_put(i2s->clk_i2s);
557 struct tegra30_i2s *i2s = dev_get_drvdata(dev);
559 regcache_mark_dirty(i2s->regmap);
566 struct tegra30_i2s *i2s = dev_get_drvdata(dev);
574 ret = regcache_sync(i2s->regmap);