Lines Matching refs:ac97
33 #define DRV_NAME "tegra20-ac97"
37 static void tegra20_ac97_codec_reset(struct snd_ac97 *ac97)
59 static void tegra20_ac97_codec_warm_reset(struct snd_ac97 *ac97)
142 static inline void tegra20_ac97_start_playback(struct tegra20_ac97 *ac97)
144 regmap_update_bits(ac97->regmap, TEGRA20_AC97_FIFO1_SCR,
148 regmap_update_bits(ac97->regmap, TEGRA20_AC97_CTRL,
155 static inline void tegra20_ac97_stop_playback(struct tegra20_ac97 *ac97)
157 regmap_update_bits(ac97->regmap, TEGRA20_AC97_FIFO1_SCR,
160 regmap_update_bits(ac97->regmap, TEGRA20_AC97_CTRL,
164 static inline void tegra20_ac97_start_capture(struct tegra20_ac97 *ac97)
166 regmap_update_bits(ac97->regmap, TEGRA20_AC97_FIFO1_SCR,
171 static inline void tegra20_ac97_stop_capture(struct tegra20_ac97 *ac97)
173 regmap_update_bits(ac97->regmap, TEGRA20_AC97_FIFO1_SCR,
180 struct tegra20_ac97 *ac97 = snd_soc_dai_get_drvdata(dai);
187 tegra20_ac97_start_playback(ac97);
189 tegra20_ac97_start_capture(ac97);
195 tegra20_ac97_stop_playback(ac97);
197 tegra20_ac97_stop_capture(ac97);
212 struct tegra20_ac97 *ac97 = snd_soc_dai_get_drvdata(dai);
214 dai->capture_dma_data = &ac97->capture_dma_data;
215 dai->playback_dma_data = &ac97->playback_dma_data;
221 .name = "tegra-ac97-pcm",
303 struct tegra20_ac97 *ac97;
308 ac97 = devm_kzalloc(&pdev->dev, sizeof(struct tegra20_ac97),
310 if (!ac97) {
314 dev_set_drvdata(&pdev->dev, ac97);
316 ac97->clk_ac97 = devm_clk_get(&pdev->dev, NULL);
317 if (IS_ERR(ac97->clk_ac97)) {
318 dev_err(&pdev->dev, "Can't retrieve ac97 clock\n");
319 ret = PTR_ERR(ac97->clk_ac97);
330 ac97->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
332 if (IS_ERR(ac97->regmap)) {
334 ret = PTR_ERR(ac97->regmap);
338 ac97->reset_gpio = of_get_named_gpio(pdev->dev.of_node,
340 if (gpio_is_valid(ac97->reset_gpio)) {
341 ret = devm_gpio_request_one(&pdev->dev, ac97->reset_gpio,
352 ac97->sync_gpio = of_get_named_gpio(pdev->dev.of_node,
354 if (!gpio_is_valid(ac97->sync_gpio)) {
359 ac97->capture_dma_data.addr = mem->start + TEGRA20_AC97_FIFO_RX1;
360 ac97->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
361 ac97->capture_dma_data.maxburst = 4;
363 ac97->playback_dma_data.addr = mem->start + TEGRA20_AC97_FIFO_TX1;
364 ac97->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
365 ac97->playback_dma_data.maxburst = 4;
367 ret = clk_prepare_enable(ac97->clk_ac97);
394 workdata = ac97;
401 clk_disable_unprepare(ac97->clk_ac97);
410 struct tegra20_ac97 *ac97 = dev_get_drvdata(&pdev->dev);
415 clk_disable_unprepare(ac97->clk_ac97);
423 { .compatible = "nvidia,tegra20-ac97", },