Lines Matching defs:dspk
33 struct tegra186_dspk *dspk = snd_soc_component_get_drvdata(codec);
35 ucontrol->value.integer.value[0] = dspk->rx_fifo_th;
44 struct tegra186_dspk *dspk = snd_soc_component_get_drvdata(codec);
47 if (value == dspk->rx_fifo_th)
50 dspk->rx_fifo_th = value;
59 struct tegra186_dspk *dspk = snd_soc_component_get_drvdata(codec);
61 ucontrol->value.enumerated.item[0] = dspk->osr_val;
70 struct tegra186_dspk *dspk = snd_soc_component_get_drvdata(codec);
73 if (value == dspk->osr_val)
76 dspk->osr_val = value;
85 struct tegra186_dspk *dspk = snd_soc_component_get_drvdata(codec);
87 ucontrol->value.enumerated.item[0] = dspk->lrsel;
96 struct tegra186_dspk *dspk = snd_soc_component_get_drvdata(codec);
99 if (value == dspk->lrsel)
102 dspk->lrsel = value;
111 struct tegra186_dspk *dspk = snd_soc_component_get_drvdata(codec);
113 ucontrol->value.enumerated.item[0] = dspk->ch_sel;
122 struct tegra186_dspk *dspk = snd_soc_component_get_drvdata(codec);
125 if (value == dspk->ch_sel)
128 dspk->ch_sel = value;
137 struct tegra186_dspk *dspk = snd_soc_component_get_drvdata(codec);
139 ucontrol->value.enumerated.item[0] = dspk->mono_to_stereo;
148 struct tegra186_dspk *dspk = snd_soc_component_get_drvdata(codec);
151 if (value == dspk->mono_to_stereo)
154 dspk->mono_to_stereo = value;
163 struct tegra186_dspk *dspk = snd_soc_component_get_drvdata(codec);
165 ucontrol->value.enumerated.item[0] = dspk->stereo_to_mono;
174 struct tegra186_dspk *dspk = snd_soc_component_get_drvdata(codec);
177 if (value == dspk->stereo_to_mono)
180 dspk->stereo_to_mono = value;
187 struct tegra186_dspk *dspk = dev_get_drvdata(dev);
189 regcache_cache_only(dspk->regmap, true);
190 regcache_mark_dirty(dspk->regmap);
192 clk_disable_unprepare(dspk->clk_dspk);
199 struct tegra186_dspk *dspk = dev_get_drvdata(dev);
202 err = clk_prepare_enable(dspk->clk_dspk);
208 regcache_cache_only(dspk->regmap, false);
209 regcache_sync(dspk->regmap);
218 struct tegra186_dspk *dspk = snd_soc_dai_get_drvdata(dai);
231 switch (dspk->ch_sel) {
263 if (dspk->rx_fifo_th > max_th)
264 dspk->rx_fifo_th = max_th;
266 cif_conf.threshold = dspk->rx_fifo_th;
267 cif_conf.mono_conv = dspk->mono_to_stereo;
268 cif_conf.stereo_conv = dspk->stereo_to_mono;
270 tegra_set_cif(dspk->regmap, TEGRA186_DSPK_RX_CIF_CTRL,
279 dspk_clk = (DSPK_OSR_FACTOR << dspk->osr_val) * srate * DSPK_CLK_RATIO;
281 err = clk_set_rate(dspk->clk_dspk, dspk_clk);
289 regmap_update_bits(dspk->regmap,
297 (dspk->osr_val << DSPK_OSR_SHIFT) |
298 ((dspk->ch_sel + 1) << CH_SEL_SHIFT) |
299 (dspk->lrsel << LRSEL_POL_SHIFT));
472 { .compatible = "nvidia,tegra186-dspk" },
480 struct tegra186_dspk *dspk;
484 dspk = devm_kzalloc(dev, sizeof(*dspk), GFP_KERNEL);
485 if (!dspk)
488 dspk->osr_val = DSPK_OSR_64;
489 dspk->lrsel = DSPK_LRSEL_LEFT;
490 dspk->ch_sel = DSPK_CH_SELECT_STEREO;
491 dspk->mono_to_stereo = 0; /* "Zero" */
493 dev_set_drvdata(dev, dspk);
495 dspk->clk_dspk = devm_clk_get(dev, "dspk");
496 if (IS_ERR(dspk->clk_dspk)) {
498 return PTR_ERR(dspk->clk_dspk);
505 dspk->regmap = devm_regmap_init_mmio(dev, regs, &tegra186_dspk_regmap);
506 if (IS_ERR(dspk->regmap)) {
508 return PTR_ERR(dspk->regmap);
511 regcache_cache_only(dspk->regmap, true);
543 .name = "tegra186-dspk",