Lines Matching refs:sai
40 { .compatible = "st,stm32f4-sai", .data = (void *)&stm32_sai_conf_f4 },
41 { .compatible = "st,stm32h7-sai", .data = (void *)&stm32_sai_conf_h7 },
47 struct stm32_sai_data *sai = dev_get_drvdata(dev);
49 clk_disable_unprepare(sai->pclk);
56 struct stm32_sai_data *sai = dev_get_drvdata(dev);
59 ret = clk_prepare_enable(sai->pclk);
61 dev_err(&sai->pdev->dev, "failed to enable clock: %d\n", ret);
68 static int stm32_sai_sync_conf_client(struct stm32_sai_data *sai, int synci)
73 ret = stm32_sai_pclk_enable(&sai->pdev->dev);
77 writel_relaxed(FIELD_PREP(SAI_GCR_SYNCIN_MASK, (synci - 1)), sai->base);
79 stm32_sai_pclk_disable(&sai->pdev->dev);
84 static int stm32_sai_sync_conf_provider(struct stm32_sai_data *sai, int synco)
90 ret = stm32_sai_pclk_enable(&sai->pdev->dev);
94 dev_dbg(&sai->pdev->dev, "Set %pOFn%s as synchro provider\n",
95 sai->pdev->dev.of_node,
98 prev_synco = FIELD_GET(SAI_GCR_SYNCOUT_MASK, readl_relaxed(sai->base));
100 dev_err(&sai->pdev->dev, "%pOFn%s already set as sync provider\n",
101 sai->pdev->dev.of_node,
103 stm32_sai_pclk_disable(&sai->pdev->dev);
107 writel_relaxed(FIELD_PREP(SAI_GCR_SYNCOUT_MASK, synco), sai->base);
109 stm32_sai_pclk_disable(&sai->pdev->dev);
153 struct stm32_sai_data *sai;
159 sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL);
160 if (!sai)
163 sai->base = devm_platform_ioremap_resource(pdev, 0);
164 if (IS_ERR(sai->base))
165 return PTR_ERR(sai->base);
169 memcpy(&sai->conf, (const struct stm32_sai_conf *)of_id->data,
174 if (!STM_SAI_IS_F4(sai)) {
175 sai->pclk = devm_clk_get(&pdev->dev, "pclk");
176 if (IS_ERR(sai->pclk)) {
177 if (PTR_ERR(sai->pclk) != -EPROBE_DEFER)
179 PTR_ERR(sai->pclk));
180 return PTR_ERR(sai->pclk);
184 sai->clk_x8k = devm_clk_get(&pdev->dev, "x8k");
185 if (IS_ERR(sai->clk_x8k)) {
186 if (PTR_ERR(sai->clk_x8k) != -EPROBE_DEFER)
188 PTR_ERR(sai->clk_x8k));
189 return PTR_ERR(sai->clk_x8k);
192 sai->clk_x11k = devm_clk_get(&pdev->dev, "x11k");
193 if (IS_ERR(sai->clk_x11k)) {
194 if (PTR_ERR(sai->clk_x11k) != -EPROBE_DEFER)
196 PTR_ERR(sai->clk_x11k));
197 return PTR_ERR(sai->clk_x11k);
201 sai->irq = platform_get_irq(pdev, 0);
202 if (sai->irq < 0)
203 return sai->irq;
218 ret = clk_prepare_enable(sai->pclk);
225 readl_relaxed(sai->base + STM_SAI_IDR));
227 val = readl_relaxed(sai->base + STM_SAI_HWCFGR);
228 sai->conf.fifo_size = FIELD_GET(SAI_HWCFGR_FIFO_SIZE, val);
229 sai->conf.has_spdif_pdm = !!FIELD_GET(SAI_HWCFGR_SPDIF_PDM,
232 val = readl_relaxed(sai->base + STM_SAI_VERR);
233 sai->conf.version = val;
239 clk_disable_unprepare(sai->pclk);
241 sai->pdev = pdev;
242 sai->set_sync = &stm32_sai_set_sync;
243 platform_set_drvdata(pdev, sai);
250 * When pins are shared by two sai sub instances, pins have to be defined
251 * in sai parent node. In this case, pins state is not managed by alsa fw.
256 struct stm32_sai_data *sai = dev_get_drvdata(dev);
263 sai->gcr = readl_relaxed(sai->base);
271 struct stm32_sai_data *sai = dev_get_drvdata(dev);
278 writel_relaxed(sai->gcr, sai->base);
293 .name = "st,stm32-sai",
304 MODULE_ALIAS("platform:st,stm32-sai");