Lines Matching refs:mcdt
14 #include "sprd-mcdt.h"
118 static void sprd_mcdt_update(struct sprd_mcdt_dev *mcdt, u32 reg, u32 val,
121 u32 orig = readl_relaxed(mcdt->base + reg);
125 writel_relaxed(tmp, mcdt->base + reg);
128 static void sprd_mcdt_dac_set_watermark(struct sprd_mcdt_dev *mcdt, u8 channel,
136 sprd_mcdt_update(mcdt, reg, water_mark,
140 static void sprd_mcdt_adc_set_watermark(struct sprd_mcdt_dev *mcdt, u8 channel,
148 sprd_mcdt_update(mcdt, reg, water_mark,
152 static void sprd_mcdt_dac_dma_enable(struct sprd_mcdt_dev *mcdt, u8 channel,
158 sprd_mcdt_update(mcdt, MCDT_DMA_EN, BIT(shift), BIT(shift));
160 sprd_mcdt_update(mcdt, MCDT_DMA_EN, 0, BIT(shift));
163 static void sprd_mcdt_adc_dma_enable(struct sprd_mcdt_dev *mcdt, u8 channel,
167 sprd_mcdt_update(mcdt, MCDT_DMA_EN, BIT(channel), BIT(channel));
169 sprd_mcdt_update(mcdt, MCDT_DMA_EN, 0, BIT(channel));
172 static void sprd_mcdt_ap_int_enable(struct sprd_mcdt_dev *mcdt, u8 channel,
176 sprd_mcdt_update(mcdt, MCDT_INT_MSK_CFG0, BIT(channel),
179 sprd_mcdt_update(mcdt, MCDT_INT_MSK_CFG0, 0, BIT(channel));
182 static void sprd_mcdt_dac_write_fifo(struct sprd_mcdt_dev *mcdt, u8 channel,
187 writel_relaxed(val, mcdt->base + reg);
190 static void sprd_mcdt_adc_read_fifo(struct sprd_mcdt_dev *mcdt, u8 channel,
195 *val = readl_relaxed(mcdt->base + reg);
198 static void sprd_mcdt_dac_dma_chn_select(struct sprd_mcdt_dev *mcdt, u8 channel,
203 sprd_mcdt_update(mcdt, MCDT_DMA_CFG0,
209 sprd_mcdt_update(mcdt, MCDT_DMA_CFG0,
215 sprd_mcdt_update(mcdt, MCDT_DMA_CFG0,
221 sprd_mcdt_update(mcdt, MCDT_DMA_CFG0,
227 sprd_mcdt_update(mcdt, MCDT_DMA_CFG0,
234 static void sprd_mcdt_adc_dma_chn_select(struct sprd_mcdt_dev *mcdt, u8 channel,
239 sprd_mcdt_update(mcdt, MCDT_DMA_CFG1,
245 sprd_mcdt_update(mcdt, MCDT_DMA_CFG1,
251 sprd_mcdt_update(mcdt, MCDT_DMA_CFG1,
257 sprd_mcdt_update(mcdt, MCDT_DMA_CFG1,
263 sprd_mcdt_update(mcdt, MCDT_DMA_CFG1,
295 static void sprd_mcdt_dac_dma_ack_select(struct sprd_mcdt_dev *mcdt, u8 channel,
313 sprd_mcdt_update(mcdt, reg, ack << shift,
317 static void sprd_mcdt_adc_dma_ack_select(struct sprd_mcdt_dev *mcdt, u8 channel,
335 sprd_mcdt_update(mcdt, reg, ack << shift,
339 static bool sprd_mcdt_chan_fifo_sts(struct sprd_mcdt_dev *mcdt, u8 channel,
385 return !!(readl_relaxed(mcdt->base + reg) & BIT(shift));
388 static void sprd_mcdt_dac_fifo_clear(struct sprd_mcdt_dev *mcdt, u8 channel)
390 sprd_mcdt_update(mcdt, MCDT_FIFO_CLR, BIT(channel), BIT(channel));
393 static void sprd_mcdt_adc_fifo_clear(struct sprd_mcdt_dev *mcdt, u8 channel)
397 sprd_mcdt_update(mcdt, MCDT_FIFO_CLR, BIT(shift), BIT(shift));
400 static u32 sprd_mcdt_dac_fifo_avail(struct sprd_mcdt_dev *mcdt, u8 channel)
403 u32 r_addr = (readl_relaxed(mcdt->base + reg) >>
405 u32 w_addr = readl_relaxed(mcdt->base + reg) & MCDT_CH_FIFO_ADDR_MASK;
413 static u32 sprd_mcdt_adc_fifo_avail(struct sprd_mcdt_dev *mcdt, u8 channel)
416 u32 r_addr = (readl_relaxed(mcdt->base + reg) >>
418 u32 w_addr = readl_relaxed(mcdt->base + reg) & MCDT_CH_FIFO_ADDR_MASK;
453 static void sprd_mcdt_chan_int_en(struct sprd_mcdt_dev *mcdt, u8 channel,
473 sprd_mcdt_update(mcdt, reg, BIT(shift), BIT(shift));
475 sprd_mcdt_update(mcdt, reg, 0, BIT(shift));
478 static void sprd_mcdt_chan_int_clear(struct sprd_mcdt_dev *mcdt, u8 channel,
497 sprd_mcdt_update(mcdt, reg, BIT(shift), BIT(shift));
500 static bool sprd_mcdt_chan_int_sts(struct sprd_mcdt_dev *mcdt, u8 channel,
519 return !!(readl_relaxed(mcdt->base + reg) & BIT(shift));
524 struct sprd_mcdt_dev *mcdt = (struct sprd_mcdt_dev *)dev_id;
527 spin_lock(&mcdt->lock);
530 if (sprd_mcdt_chan_int_sts(mcdt, i, MCDT_ADC_FIFO_AF_INT)) {
531 struct sprd_mcdt_chan *chan = &mcdt->chan[i];
533 sprd_mcdt_chan_int_clear(mcdt, i, MCDT_ADC_FIFO_AF_INT);
540 if (sprd_mcdt_chan_int_sts(mcdt, i, MCDT_DAC_FIFO_AE_INT)) {
542 &mcdt->chan[i + MCDT_ADC_CHANNEL_NUM];
544 sprd_mcdt_chan_int_clear(mcdt, i, MCDT_DAC_FIFO_AE_INT);
550 spin_unlock(&mcdt->lock);
571 struct sprd_mcdt_dev *mcdt = chan->mcdt;
576 spin_lock_irqsave(&mcdt->lock, flags);
579 dev_err(mcdt->dev,
581 spin_unlock_irqrestore(&mcdt->lock, flags);
585 if (sprd_mcdt_chan_fifo_sts(mcdt, chan->id, MCDT_DAC_FIFO_REAL_FULL)) {
586 dev_err(mcdt->dev, "Channel fifo is full now\n");
587 spin_unlock_irqrestore(&mcdt->lock, flags);
591 avail = sprd_mcdt_dac_fifo_avail(mcdt, chan->id);
593 dev_err(mcdt->dev,
595 spin_unlock_irqrestore(&mcdt->lock, flags);
600 sprd_mcdt_dac_write_fifo(mcdt, chan->id, *buf++);
602 spin_unlock_irqrestore(&mcdt->lock, flags);
622 struct sprd_mcdt_dev *mcdt = chan->mcdt;
627 spin_lock_irqsave(&mcdt->lock, flags);
630 dev_err(mcdt->dev, "Can not read data when DMA mode enabled\n");
631 spin_unlock_irqrestore(&mcdt->lock, flags);
635 if (sprd_mcdt_chan_fifo_sts(mcdt, chan->id, MCDT_ADC_FIFO_REAL_EMPTY)) {
636 dev_err(mcdt->dev, "Channel fifo is empty\n");
637 spin_unlock_irqrestore(&mcdt->lock, flags);
641 avail = sprd_mcdt_adc_fifo_avail(mcdt, chan->id);
646 sprd_mcdt_adc_read_fifo(mcdt, chan->id, buf++);
648 spin_unlock_irqrestore(&mcdt->lock, flags);
674 struct sprd_mcdt_dev *mcdt = chan->mcdt;
678 spin_lock_irqsave(&mcdt->lock, flags);
681 dev_err(mcdt->dev, "Failed to set interrupt mode.\n");
682 spin_unlock_irqrestore(&mcdt->lock, flags);
688 sprd_mcdt_adc_fifo_clear(mcdt, chan->id);
689 sprd_mcdt_adc_set_watermark(mcdt, chan->id, water_mark,
691 sprd_mcdt_chan_int_en(mcdt, chan->id,
693 sprd_mcdt_ap_int_enable(mcdt, chan->id, true);
697 sprd_mcdt_dac_fifo_clear(mcdt, chan->id);
698 sprd_mcdt_dac_set_watermark(mcdt, chan->id,
700 sprd_mcdt_chan_int_en(mcdt, chan->id,
702 sprd_mcdt_ap_int_enable(mcdt, chan->id, true);
706 dev_err(mcdt->dev, "Unsupported channel type\n");
715 spin_unlock_irqrestore(&mcdt->lock, flags);
727 struct sprd_mcdt_dev *mcdt = chan->mcdt;
730 spin_lock_irqsave(&mcdt->lock, flags);
733 spin_unlock_irqrestore(&mcdt->lock, flags);
739 sprd_mcdt_chan_int_en(mcdt, chan->id,
741 sprd_mcdt_chan_int_clear(mcdt, chan->id, MCDT_ADC_FIFO_AF_INT);
742 sprd_mcdt_ap_int_enable(mcdt, chan->id, false);
746 sprd_mcdt_chan_int_en(mcdt, chan->id,
748 sprd_mcdt_chan_int_clear(mcdt, chan->id, MCDT_DAC_FIFO_AE_INT);
749 sprd_mcdt_ap_int_enable(mcdt, chan->id, false);
757 spin_unlock_irqrestore(&mcdt->lock, flags);
777 struct sprd_mcdt_dev *mcdt = chan->mcdt;
781 spin_lock_irqsave(&mcdt->lock, flags);
785 dev_err(mcdt->dev, "Failed to set DMA mode\n");
786 spin_unlock_irqrestore(&mcdt->lock, flags);
792 sprd_mcdt_adc_fifo_clear(mcdt, chan->id);
793 sprd_mcdt_adc_set_watermark(mcdt, chan->id,
795 sprd_mcdt_adc_dma_enable(mcdt, chan->id, true);
796 sprd_mcdt_adc_dma_chn_select(mcdt, chan->id, dma_chan);
797 sprd_mcdt_adc_dma_ack_select(mcdt, chan->id, dma_chan);
801 sprd_mcdt_dac_fifo_clear(mcdt, chan->id);
802 sprd_mcdt_dac_set_watermark(mcdt, chan->id,
804 sprd_mcdt_dac_dma_enable(mcdt, chan->id, true);
805 sprd_mcdt_dac_dma_chn_select(mcdt, chan->id, dma_chan);
806 sprd_mcdt_dac_dma_ack_select(mcdt, chan->id, dma_chan);
810 dev_err(mcdt->dev, "Unsupported channel type\n");
817 spin_unlock_irqrestore(&mcdt->lock, flags);
829 struct sprd_mcdt_dev *mcdt = chan->mcdt;
832 spin_lock_irqsave(&mcdt->lock, flags);
835 spin_unlock_irqrestore(&mcdt->lock, flags);
841 sprd_mcdt_adc_dma_enable(mcdt, chan->id, false);
842 sprd_mcdt_adc_fifo_clear(mcdt, chan->id);
846 sprd_mcdt_dac_dma_enable(mcdt, chan->id, false);
847 sprd_mcdt_dac_fifo_clear(mcdt, chan->id);
855 spin_unlock_irqrestore(&mcdt->lock, flags);
914 static void sprd_mcdt_init_chans(struct sprd_mcdt_dev *mcdt,
920 struct sprd_mcdt_chan *chan = &mcdt->chan[i];
933 chan->mcdt = mcdt;
944 struct sprd_mcdt_dev *mcdt;
948 mcdt = devm_kzalloc(&pdev->dev, sizeof(*mcdt), GFP_KERNEL);
949 if (!mcdt)
953 mcdt->base = devm_ioremap_resource(&pdev->dev, res);
954 if (IS_ERR(mcdt->base))
955 return PTR_ERR(mcdt->base);
957 mcdt->dev = &pdev->dev;
958 spin_lock_init(&mcdt->lock);
959 platform_set_drvdata(pdev, mcdt);
966 0, "sprd-mcdt", mcdt);
972 sprd_mcdt_init_chans(mcdt, res);
992 { .compatible = "sprd,sc9860-mcdt", },
1001 .name = "sprd-mcdt",