Lines Matching refs:sdev
37 int hda_dsp_core_reset_enter(struct snd_sof_dev *sdev, unsigned int core_mask)
45 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
50 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
56 dev_err(sdev->dev,
63 adspcs = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
67 dev_err(sdev->dev,
76 int hda_dsp_core_reset_leave(struct snd_sof_dev *sdev, unsigned int core_mask)
83 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
90 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
97 dev_err(sdev->dev,
104 adspcs = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
107 dev_err(sdev->dev,
116 int hda_dsp_core_stall_reset(struct snd_sof_dev *sdev, unsigned int core_mask)
119 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
125 return hda_dsp_core_reset_enter(sdev, core_mask);
128 int hda_dsp_core_run(struct snd_sof_dev *sdev, unsigned int core_mask)
133 ret = hda_dsp_core_reset_leave(sdev, core_mask);
138 dev_dbg(sdev->dev, "unstall/run core: core_mask = %x\n", core_mask);
139 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
145 if (!hda_dsp_core_is_enabled(sdev, core_mask)) {
146 hda_dsp_core_stall_reset(sdev, core_mask);
147 dev_err(sdev->dev, "error: DSP start core failed: core_mask %x\n",
159 int hda_dsp_core_power_up(struct snd_sof_dev *sdev, unsigned int core_mask)
166 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPCS,
172 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
178 dev_err(sdev->dev,
185 adspcs = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
189 dev_err(sdev->dev,
198 int hda_dsp_core_power_down(struct snd_sof_dev *sdev, unsigned int core_mask)
204 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
208 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
214 dev_err(sdev->dev,
221 bool hda_dsp_core_is_enabled(struct snd_sof_dev *sdev,
227 val = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPCS);
241 dev_dbg(sdev->dev, "DSP core(s) enabled? %d : core_mask %x\n",
247 int hda_dsp_enable_core(struct snd_sof_dev *sdev, unsigned int core_mask)
249 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
257 if (!core_mask || hda_dsp_core_is_enabled(sdev, core_mask))
261 ret = hda_dsp_core_power_up(sdev, core_mask);
263 dev_err(sdev->dev, "error: dsp core power up failed: core_mask %x\n",
268 return hda_dsp_core_run(sdev, core_mask);
271 int hda_dsp_core_reset_power_down(struct snd_sof_dev *sdev,
274 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
286 ret = hda_dsp_core_stall_reset(sdev, core_mask);
288 dev_err(sdev->dev, "error: dsp core reset failed: core_mask %x\n",
294 ret = hda_dsp_core_power_down(sdev, core_mask);
296 dev_err(sdev->dev, "error: dsp core power down fail mask %x: %d\n",
302 if (hda_dsp_core_is_enabled(sdev, core_mask)) {
303 dev_err(sdev->dev, "error: dsp core disable fail mask %x: %d\n",
311 void hda_dsp_ipc_int_enable(struct snd_sof_dev *sdev)
313 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
317 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl,
322 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIC,
326 void hda_dsp_ipc_int_disable(struct snd_sof_dev *sdev)
328 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
332 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIC,
336 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl,
340 static int hda_dsp_wait_d0i3c_done(struct snd_sof_dev *sdev)
342 struct hdac_bus *bus = sof_to_bus(sdev);
354 static int hda_dsp_send_pm_gate_ipc(struct snd_sof_dev *sdev, u32 flags)
367 return sof_ipc_tx_message_no_pm(sdev->ipc, pm_gate.hdr.cmd,
372 static int hda_dsp_update_d0i3c_register(struct snd_sof_dev *sdev, u8 value)
374 struct hdac_bus *bus = sof_to_bus(sdev);
378 ret = hda_dsp_wait_d0i3c_done(sdev);
388 ret = hda_dsp_wait_d0i3c_done(sdev);
400 static int hda_dsp_set_D0_state(struct snd_sof_dev *sdev,
414 switch (sdev->dsp_power_state.state) {
422 dev_err(sdev->dev, "error: transition from %d to %d not allowed\n",
423 sdev->dsp_power_state.state, target_state->state);
437 if (!sdev->dtrace_is_supported ||
439 sdev->system_suspend_target != SOF_SUSPEND_NONE)
447 ret = hda_dsp_update_d0i3c_register(sdev, value);
456 ret = hda_dsp_send_pm_gate_ipc(sdev, flags);
458 dev_err(sdev->dev,
473 hda_dsp_update_d0i3c_register(sdev, value);
479 static void hda_dsp_state_log(struct snd_sof_dev *sdev)
481 switch (sdev->dsp_power_state.state) {
483 switch (sdev->dsp_power_state.substate) {
485 dev_dbg(sdev->dev, "Current DSP power state: D0I0\n");
488 dev_dbg(sdev->dev, "Current DSP power state: D0I3\n");
491 dev_dbg(sdev->dev, "Unknown DSP D0 substate: %d\n",
492 sdev->dsp_power_state.substate);
497 dev_dbg(sdev->dev, "Current DSP power state: D1\n");
500 dev_dbg(sdev->dev, "Current DSP power state: D2\n");
503 dev_dbg(sdev->dev, "Current DSP power state: D3_HOT\n");
506 dev_dbg(sdev->dev, "Current DSP power state: D3\n");
509 dev_dbg(sdev->dev, "Current DSP power state: D3_COLD\n");
512 dev_dbg(sdev->dev, "Unknown DSP power state: %d\n",
513 sdev->dsp_power_state.state);
525 int hda_dsp_set_power_state(struct snd_sof_dev *sdev,
538 sdev->system_suspend_target == SOF_SUSPEND_S0IX)
545 if (target_state->state == sdev->dsp_power_state.state &&
546 target_state->substate == sdev->dsp_power_state.substate)
552 ret = hda_dsp_set_D0_state(sdev, target_state);
556 if (sdev->dsp_power_state.state == SOF_DSP_PM_D0 &&
557 sdev->dsp_power_state.substate == SOF_HDA_DSP_PM_D0I0)
560 dev_err(sdev->dev,
562 sdev->dsp_power_state.state, target_state->state);
565 dev_err(sdev->dev, "error: target state unsupported %d\n",
570 dev_err(sdev->dev,
576 sdev->dsp_power_state = *target_state;
577 hda_dsp_state_log(sdev);
611 static int hda_suspend(struct snd_sof_dev *sdev, bool runtime_suspend)
613 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
616 struct hdac_bus *bus = sof_to_bus(sdev);
620 hda_sdw_int_enable(sdev, false);
623 hda_dsp_ipc_int_disable(sdev);
627 hda_codec_jack_wake_enable(sdev);
634 ret = hda_dsp_core_reset_power_down(sdev, chip->host_managed_cores_mask);
636 dev_err(sdev->dev,
642 hda_dsp_ctrl_ppcap_enable(sdev, false);
643 hda_dsp_ctrl_ppcap_int_enable(sdev, false);
646 hda_dsp_ctrl_stop_chip(sdev);
649 snd_sof_pci_update_bits(sdev, PCI_PGCTL,
653 ret = hda_dsp_ctrl_link_reset(sdev, true);
655 dev_err(sdev->dev,
661 hda_codec_i915_display_power(sdev, false);
666 static int hda_resume(struct snd_sof_dev *sdev, bool runtime_resume)
669 struct hdac_bus *bus = sof_to_bus(sdev);
675 hda_codec_i915_display_power(sdev, true);
681 snd_sof_pci_update_bits(sdev, PCI_TCSEL, 0x07, 0);
684 ret = hda_dsp_ctrl_init_chip(sdev, true);
686 dev_err(sdev->dev,
694 if (sdev->system_suspend_target == SOF_SUSPEND_NONE)
695 hda_codec_jack_check(sdev);
710 hda_dsp_ctrl_ppcap_enable(sdev, true);
711 hda_dsp_ctrl_ppcap_int_enable(sdev, true);
716 int hda_dsp_resume(struct snd_sof_dev *sdev)
718 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
719 struct pci_dev *pci = to_pci_dev(sdev->dev);
725 struct hdac_bus *bus = sof_to_bus(sdev);
731 if (sdev->dsp_power_state.state == SOF_DSP_PM_D0) {
732 hda_codec_i915_display_power(sdev, true);
740 dev_dbg(sdev->dev,
754 ret = snd_sof_dsp_set_power_state(sdev, &target_state);
756 dev_err(sdev->dev, "error: setting dsp state %d substate %d\n",
763 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
774 ret = hda_resume(sdev, false);
778 return snd_sof_dsp_set_power_state(sdev, &target_state);
781 int hda_dsp_runtime_resume(struct snd_sof_dev *sdev)
789 ret = hda_resume(sdev, true);
793 return snd_sof_dsp_set_power_state(sdev, &target_state);
796 int hda_dsp_runtime_idle(struct snd_sof_dev *sdev)
798 struct hdac_bus *hbus = sof_to_bus(sdev);
801 dev_dbg(sdev->dev, "some codecs still powered (%08X), not idle\n",
809 int hda_dsp_runtime_suspend(struct snd_sof_dev *sdev)
811 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
821 ret = hda_suspend(sdev, true);
825 return snd_sof_dsp_set_power_state(sdev, &target_state);
828 int hda_dsp_suspend(struct snd_sof_dev *sdev, u32 target_state)
830 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
831 struct hdac_bus *bus = sof_to_bus(sdev);
832 struct pci_dev *pci = to_pci_dev(sdev->dev);
845 hda_codec_i915_display_power(sdev, false);
848 ret = snd_sof_dsp_set_power_state(sdev, &target_dsp_state);
850 dev_err(sdev->dev, "error: setting dsp state %d substate %d\n",
858 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
871 dev_dbg(sdev->dev,
885 ret = hda_suspend(sdev, false);
891 return snd_sof_dsp_set_power_state(sdev, &target_dsp_state);
894 int hda_dsp_set_hw_params_upon_resume(struct snd_sof_dev *sdev)
897 struct hdac_bus *bus = sof_to_bus(sdev);
942 struct snd_sof_dev *sdev = dev_get_drvdata(bus->dev);
949 if (snd_sof_dsp_only_d0i3_compatible_stream_active(sdev))
959 ret = snd_sof_dsp_set_power_state(sdev, &target_state);
961 dev_err_ratelimited(sdev->dev,