Lines Matching defs:sdev
35 int hda_dsp_ctrl_link_reset(struct snd_sof_dev *sdev, bool reset)
45 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_GCTL,
51 gctl = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_GCTL);
58 dev_err(sdev->dev, "error: failed to %s HDA controller gctl 0x%x\n",
63 int hda_dsp_ctrl_get_caps(struct snd_sof_dev *sdev)
65 struct hdac_bus *bus = sof_to_bus(sdev);
74 ret = hda_dsp_ctrl_link_reset(sdev, true);
77 ret = hda_dsp_ctrl_link_reset(sdev, false);
81 offset = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_LLCH);
84 dev_dbg(sdev->dev, "checking for capabilities at offset 0x%x\n",
87 cap = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, offset);
98 dev_dbg(sdev->dev, "found DSP capability at 0x%x\n",
101 sdev->bar[HDA_DSP_PP_BAR] = bus->ppcap;
104 dev_dbg(sdev->dev, "found SPIB capability at 0x%x\n",
107 sdev->bar[HDA_DSP_SPIB_BAR] = bus->spbcap;
110 dev_dbg(sdev->dev, "found DRSM capability at 0x%x\n",
113 sdev->bar[HDA_DSP_DRSM_BAR] = bus->drsmcap;
116 dev_dbg(sdev->dev, "found GTS capability at 0x%x\n",
121 dev_dbg(sdev->dev, "found ML capability at 0x%x\n",
126 dev_dbg(sdev->dev, "found capability %d at 0x%x\n",
137 void hda_dsp_ctrl_ppcap_enable(struct snd_sof_dev *sdev, bool enable)
141 snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
145 void hda_dsp_ctrl_ppcap_int_enable(struct snd_sof_dev *sdev, bool enable)
149 snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
153 void hda_dsp_ctrl_misc_clock_gating(struct snd_sof_dev *sdev, bool enable)
157 snd_sof_pci_update_bits(sdev, PCI_CGCTL, PCI_CGCTL_MISCBDCGE_MASK, val);
165 int hda_dsp_ctrl_clock_power_gating(struct snd_sof_dev *sdev, bool enable)
171 snd_sof_pci_update_bits(sdev, PCI_CGCTL, PCI_CGCTL_ADSPDCGE, val);
175 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, HDA_VS_INTEL_EM2,
180 snd_sof_pci_update_bits(sdev, PCI_PGCTL, PCI_PGCTL_ADSPPGD, val);
185 int hda_dsp_ctrl_init_chip(struct snd_sof_dev *sdev, bool full_reset)
187 struct hdac_bus *bus = sof_to_bus(sdev);
200 hda_dsp_ctrl_misc_clock_gating(sdev, false);
204 ret = hda_dsp_ctrl_link_reset(sdev, true);
206 dev_err(sdev->dev, "error: failed to reset HDA controller\n");
213 ret = hda_dsp_ctrl_link_reset(sdev, false);
215 dev_err(sdev->dev, "error: failed to exit HDA controller reset\n");
249 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
255 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_WAKESTS,
264 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTSTS,
273 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL,
279 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_ADSP_DPLBASE,
281 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_ADSP_DPUBASE,
294 hda_dsp_ctrl_misc_clock_gating(sdev, true);
302 void hda_dsp_ctrl_stop_chip(struct snd_sof_dev *sdev)
304 struct hdac_bus *bus = sof_to_bus(sdev);
314 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
322 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL,
326 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL,
333 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
339 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_WAKESTS,
348 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTSTS,
357 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
359 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,