Lines Matching defs:sdev
85 static void byt_host_done(struct snd_sof_dev *sdev);
86 static void byt_dsp_done(struct snd_sof_dev *sdev);
87 static void byt_get_reply(struct snd_sof_dev *sdev);
93 static void byt_get_registers(struct snd_sof_dev *sdev,
98 u32 offset = sdev->dsp_oops_offset;
101 sof_mailbox_read(sdev, offset, xoops, sizeof(*xoops));
107 dev_err(sdev->dev, "invalid header size 0x%x. FW oops is bogus\n",
112 sof_mailbox_read(sdev, offset, panic_info, sizeof(*panic_info));
116 sof_mailbox_read(sdev, offset, stack, stack_words * sizeof(u32));
119 static void byt_dump(struct snd_sof_dev *sdev, u32 flags)
127 status = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IPCD);
128 panic = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IPCX);
129 byt_get_registers(sdev, &xoops, &panic_info, stack,
131 snd_sof_get_status(sdev, status, panic, &xoops, &panic_info, stack,
135 imrx = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IMRX);
136 imrd = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IMRD);
137 dev_err(sdev->dev,
141 dev_err(sdev->dev,
145 dev_err(sdev->dev,
149 dev_err(sdev->dev,
162 struct snd_sof_dev *sdev = context;
166 ipcx = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IPCX);
167 ipcd = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IPCD);
172 snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR,
182 snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR,
194 struct snd_sof_dev *sdev = context;
197 ipcx = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IPCX);
198 ipcd = snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_IPCD);
203 spin_lock_irq(&sdev->ipc_lock);
212 byt_get_reply(sdev);
213 snd_sof_ipc_reply(sdev, ipcx);
215 byt_dsp_done(sdev);
217 spin_unlock_irq(&sdev->ipc_lock);
225 snd_sof_dsp_panic(sdev, BYT_PANIC_OFFSET(ipcd) +
228 snd_sof_ipc_msgs_rx(sdev);
231 byt_host_done(sdev);
237 static int byt_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg)
240 snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, SHIM_IMRX,
244 sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data,
246 snd_sof_dsp_write64(sdev, BYT_DSP_BAR, SHIM_IPCX, SHIM_BYT_IPCX_BUSY);
251 static void byt_get_reply(struct snd_sof_dev *sdev)
253 struct snd_sof_ipc_msg *msg = sdev->msg;
263 dev_warn(sdev->dev, "unexpected ipc interrupt raised!\n");
268 sof_mailbox_read(sdev, sdev->host_box.offset, &reply, sizeof(reply));
276 dev_err(sdev->dev, "error: reply expected %zu got %u bytes\n",
283 sof_mailbox_read(sdev, sdev->host_box.offset,
290 static int byt_get_mailbox_offset(struct snd_sof_dev *sdev)
295 static int byt_get_window_offset(struct snd_sof_dev *sdev, u32 id)
300 static void byt_host_done(struct snd_sof_dev *sdev)
303 snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, SHIM_IPCD,
309 snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, SHIM_IMRX,
313 static void byt_dsp_done(struct snd_sof_dev *sdev)
316 snd_sof_dsp_update_bits64_unlocked(sdev, BYT_DSP_BAR, SHIM_IPCX,
324 static int byt_run(struct snd_sof_dev *sdev)
329 snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_CSR,
332 if (!(snd_sof_dsp_read64(sdev, BYT_DSP_BAR, SHIM_CSR) &
338 dev_err(sdev->dev, "error: unable to run DSP firmware\n");
339 byt_dump(sdev, SOF_DBG_REGS | SOF_DBG_MBOX);
347 static int byt_reset(struct snd_sof_dev *sdev)
350 snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_CSR,
359 snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_CSR,
365 static const char *fixup_tplg_name(struct snd_sof_dev *sdev,
373 filename = devm_kstrdup(sdev->dev, sof_tplg_filename, GFP_KERNEL);
380 tplg_filename = devm_kasprintf(sdev->dev, GFP_KERNEL,
389 static void byt_machine_select(struct snd_sof_dev *sdev)
391 struct snd_sof_pdata *sof_pdata = sdev->pdata;
399 dev_warn(sdev->dev, "warning: No matching ASoC machine driver found\n");
403 pdev = to_platform_device(sdev->dev);
405 dev_dbg(sdev->dev,
408 tplg_filename = fixup_tplg_name(sdev,
416 dev_dbg(sdev->dev,
511 static int tangier_pci_probe(struct snd_sof_dev *sdev)
513 struct snd_sof_pdata *pdata = sdev->pdata;
515 struct pci_dev *pci = to_pci_dev(sdev->dev);
522 dev_err(sdev->dev, "error: failed to set DMA mask %d\n", ret);
530 dev_dbg(sdev->dev, "LPE PHY base at 0x%x size 0x%x", base, size);
531 sdev->bar[BYT_DSP_BAR] = devm_ioremap(sdev->dev, base, size);
532 if (!sdev->bar[BYT_DSP_BAR]) {
533 dev_err(sdev->dev, "error: failed to ioremap LPE base 0x%x size 0x%x\n",
537 dev_dbg(sdev->dev, "LPE VADDR %p\n", sdev->bar[BYT_DSP_BAR]);
548 dev_info(sdev->dev, "IMR not set by BIOS. Ignoring\n");
552 dev_dbg(sdev->dev, "IMR base at 0x%x size 0x%x", base, size);
553 sdev->bar[BYT_IMR_BAR] = devm_ioremap(sdev->dev, base, size);
554 if (!sdev->bar[BYT_IMR_BAR]) {
555 dev_err(sdev->dev, "error: failed to ioremap IMR base 0x%x size 0x%x\n",
559 dev_dbg(sdev->dev, "IMR VADDR %p\n", sdev->bar[BYT_IMR_BAR]);
563 sdev->ipc_irq = pci->irq;
564 dev_dbg(sdev->dev, "using IRQ %d\n", sdev->ipc_irq);
565 ret = devm_request_threaded_irq(sdev->dev, sdev->ipc_irq,
567 0, "AudioDSP", sdev);
569 dev_err(sdev->dev, "error: failed to register IRQ %d\n",
570 sdev->ipc_irq);
575 snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRX,
580 sdev->dsp_box.offset = MBOX_OFFSET;
662 static void byt_reset_dsp_disable_int(struct snd_sof_dev *sdev)
665 snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRX, 0x3, 0x3);
666 snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRD, 0x3, 0x3);
669 snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_CSR,
674 static int byt_suspend(struct snd_sof_dev *sdev, u32 target_state)
676 byt_reset_dsp_disable_int(sdev);
681 static int byt_resume(struct snd_sof_dev *sdev)
684 snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRX,
691 static int byt_remove(struct snd_sof_dev *sdev)
693 byt_reset_dsp_disable_int(sdev);
725 static int byt_acpi_probe(struct snd_sof_dev *sdev)
727 struct snd_sof_pdata *pdata = sdev->pdata;
730 container_of(sdev->dev, struct platform_device, dev);
736 ret = dma_coerce_mask_and_coherent(sdev->dev, DMA_BIT_MASK(31));
738 dev_err(sdev->dev, "error: failed to set DMA mask %d\n", ret);
749 dev_err(sdev->dev, "error: failed to get LPE base at idx %d\n",
754 dev_dbg(sdev->dev, "LPE PHY base at 0x%x size 0x%x", base, size);
755 sdev->bar[BYT_DSP_BAR] = devm_ioremap(sdev->dev, base, size);
756 if (!sdev->bar[BYT_DSP_BAR]) {
757 dev_err(sdev->dev, "error: failed to ioremap LPE base 0x%x size 0x%x\n",
761 dev_dbg(sdev->dev, "LPE VADDR %p\n", sdev->bar[BYT_DSP_BAR]);
764 sdev->mmio_bar = BYT_DSP_BAR;
765 sdev->mailbox_bar = BYT_DSP_BAR;
777 dev_err(sdev->dev, "error: failed to get IMR base at idx %d\n",
784 dev_info(sdev->dev, "IMR not set by BIOS. Ignoring\n");
788 dev_dbg(sdev->dev, "IMR base at 0x%x size 0x%x", base, size);
789 sdev->bar[BYT_IMR_BAR] = devm_ioremap(sdev->dev, base, size);
790 if (!sdev->bar[BYT_IMR_BAR]) {
791 dev_err(sdev->dev, "error: failed to ioremap IMR base 0x%x size 0x%x\n",
795 dev_dbg(sdev->dev, "IMR VADDR %p\n", sdev->bar[BYT_IMR_BAR]);
799 sdev->ipc_irq = platform_get_irq(pdev, desc->irqindex_host_ipc);
800 if (sdev->ipc_irq < 0)
801 return sdev->ipc_irq;
803 dev_dbg(sdev->dev, "using IRQ %d\n", sdev->ipc_irq);
804 ret = devm_request_threaded_irq(sdev->dev, sdev->ipc_irq,
806 IRQF_SHARED, "AudioDSP", sdev);
808 dev_err(sdev->dev, "error: failed to register IRQ %d\n",
809 sdev->ipc_irq);
814 snd_sof_dsp_update_bits64(sdev, BYT_DSP_BAR, SHIM_IMRX,
819 sdev->dsp_box.offset = MBOX_OFFSET;