Lines Matching defs:ssicr
133 unsigned long ssicr = SSIREG(SSICR);
140 pr_debug("ssi_hw_params() enter\nssicr was %08lx\n", ssicr);
143 ssicr &= ~(CR_TRMD | CR_CHNL_MASK | CR_DWL_MASK | CR_PDTA |
148 ssicr |= CR_TRMD; /* transmit */
155 ssicr |= ((channels >> 1) - 1) << CR_CHNL_SHIFT;
166 ssicr |= i << CR_DWL_SHIFT;
184 /*ssicr |= CR_PDTA;*/ /* cpu/data endianness ? */
195 ssicr |= i << CR_SWL_SHIFT;
202 SSIREG(SSICR) = ssicr;
204 pr_debug("ssi_hw_params() leave\nssicr is now %08lx\n", ssicr);
225 unsigned long ssicr;
229 ssicr = SSIREG(SSICR) & ~CR_CKDIV_MASK;
235 SSIREG(SSICR) = ssicr | (i << CR_CKDIV_SHIFT);
248 unsigned long ssicr = SSIREG(SSICR);
250 pr_debug("ssi_set_fmt()\nssicr was 0x%08lx\n", ssicr);
252 ssicr &= ~(CR_DEL | CR_PDTA | CR_BREN | CR_SWSP | CR_SCKP |
259 ssicr |= CR_DEL | CR_PDTA;
262 ssicr |= CR_DEL;
273 ssicr |= CR_BREN;
279 ssicr |= CR_SCKP; /* sample data at low clkedge */
282 ssicr |= CR_SCKP | CR_SWSP;
287 ssicr |= CR_SWSP; /* word select starts low */
298 ssicr |= CR_SCK_MASTER;
301 ssicr |= CR_SWS_MASTER;
304 ssicr |= CR_SWS_MASTER | CR_SCK_MASTER;
311 SSIREG(SSICR) = ssicr;
312 pr_debug("ssi_set_fmt() leave\nssicr is now 0x%08lx\n", ssicr);