Lines Matching refs:SSICR
25 * SSICR
243 * It will set SSIWSR.CONT here, but SSICR.CKDV = 000
245 * SSICR.CKDV = 000 is not allowed either).
246 * Skip it. See SSICR.CKDV
325 * SSICR : FORCE, SCKD, SWSD
423 * The SWL and DWL bits in SSICR should be fixed at 32-bit
496 rsnd_mod_write(mod, SSICR, ssi->cr_own |
648 rsnd_mod_write(mod, SSICR, ssi->cr_own |
678 rsnd_mod_write(mod, SSICR, cr | ssi->cr_en);
692 rsnd_mod_write(mod, SSICR, cr); /* disabled all */