Lines Matching defs:i2s
24 #define DRV_NAME "rockchip-i2s"
56 struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
58 regcache_cache_only(i2s->regmap, true);
59 clk_disable_unprepare(i2s->mclk);
66 struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
69 ret = clk_prepare_enable(i2s->mclk);
71 dev_err(i2s->dev, "clock enable failed %d\n", ret);
75 regcache_cache_only(i2s->regmap, false);
76 regcache_mark_dirty(i2s->regmap);
78 ret = regcache_sync(i2s->regmap);
80 clk_disable_unprepare(i2s->mclk);
90 static void rockchip_snd_txctrl(struct rk_i2s_dev *i2s, int on)
96 regmap_update_bits(i2s->regmap, I2S_DMACR,
99 regmap_update_bits(i2s->regmap, I2S_XFER,
103 i2s->tx_start = true;
105 i2s->tx_start = false;
107 regmap_update_bits(i2s->regmap, I2S_DMACR,
110 if (!i2s->rx_start) {
111 regmap_update_bits(i2s->regmap, I2S_XFER,
118 regmap_update_bits(i2s->regmap, I2S_CLR,
122 regmap_read(i2s->regmap, I2S_CLR, &val);
126 regmap_read(i2s->regmap, I2S_CLR, &val);
129 dev_warn(i2s->dev, "fail to clear\n");
137 static void rockchip_snd_rxctrl(struct rk_i2s_dev *i2s, int on)
143 regmap_update_bits(i2s->regmap, I2S_DMACR,
146 regmap_update_bits(i2s->regmap, I2S_XFER,
150 i2s->rx_start = true;
152 i2s->rx_start = false;
154 regmap_update_bits(i2s->regmap, I2S_DMACR,
157 if (!i2s->tx_start) {
158 regmap_update_bits(i2s->regmap, I2S_XFER,
165 regmap_update_bits(i2s->regmap, I2S_CLR,
169 regmap_read(i2s->regmap, I2S_CLR, &val);
173 regmap_read(i2s->regmap, I2S_CLR, &val);
176 dev_warn(i2s->dev, "fail to clear\n");
187 struct rk_i2s_dev *i2s = to_info(cpu_dai);
197 i2s->is_master_mode = true;
201 i2s->is_master_mode = false;
208 regmap_update_bits(i2s->regmap, I2S_CKR, mask, val);
223 regmap_update_bits(i2s->regmap, I2S_CKR, mask, val);
247 regmap_update_bits(i2s->regmap, I2S_TXCR, mask, val);
271 regmap_update_bits(i2s->regmap, I2S_RXCR, mask, val);
283 struct rk_i2s_dev *i2s = to_info(dai);
288 if (i2s->is_master_mode) {
289 mclk_rate = clk_get_rate(i2s->mclk);
296 regmap_update_bits(i2s->regmap, I2S_CKR,
300 regmap_update_bits(i2s->regmap, I2S_CKR,
341 dev_err(i2s->dev, "invalid channel: %d\n",
347 regmap_update_bits(i2s->regmap, I2S_RXCR,
351 regmap_update_bits(i2s->regmap, I2S_TXCR,
355 if (!IS_ERR(i2s->grf) && i2s->pins) {
356 regmap_read(i2s->regmap, I2S_TXCR, &val);
374 val <<= i2s->pins->shift;
375 val |= (I2S_IO_DIRECTION_MASK << i2s->pins->shift) << 16;
376 regmap_write(i2s->grf, i2s->pins->reg_offset, val);
379 regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_TDL_MASK,
381 regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_RDL_MASK,
388 regmap_update_bits(i2s->regmap, I2S_CKR,
397 struct rk_i2s_dev *i2s = to_info(dai);
405 rockchip_snd_rxctrl(i2s, 1);
407 rockchip_snd_txctrl(i2s, 1);
413 rockchip_snd_rxctrl(i2s, 0);
415 rockchip_snd_txctrl(i2s, 0);
428 struct rk_i2s_dev *i2s = to_info(cpu_dai);
434 ret = clk_set_rate(i2s->mclk, freq);
436 dev_err(i2s->dev, "Fail to set mclk %d\n", ret);
443 struct rk_i2s_dev *i2s = snd_soc_dai_get_drvdata(dai);
445 dai->capture_dma_data = &i2s->capture_dma_data;
446 dai->playback_dma_data = &i2s->playback_dma_data;
579 { .compatible = "rockchip,rk3066-i2s", },
580 { .compatible = "rockchip,rk3188-i2s", },
581 { .compatible = "rockchip,rk3288-i2s", },
582 { .compatible = "rockchip,rk3399-i2s", .data = &rk3399_i2s_pins },
590 struct rk_i2s_dev *i2s;
597 i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
598 if (!i2s)
601 i2s->dev = &pdev->dev;
603 i2s->grf = syscon_regmap_lookup_by_phandle(node, "rockchip,grf");
604 if (!IS_ERR(i2s->grf)) {
609 i2s->pins = of_id->data;
613 i2s->hclk = devm_clk_get(&pdev->dev, "i2s_hclk");
614 if (IS_ERR(i2s->hclk)) {
615 dev_err(&pdev->dev, "Can't retrieve i2s bus clock\n");
616 return PTR_ERR(i2s->hclk);
618 ret = clk_prepare_enable(i2s->hclk);
620 dev_err(i2s->dev, "hclock enable failed %d\n", ret);
624 i2s->mclk = devm_clk_get(&pdev->dev, "i2s_clk");
625 if (IS_ERR(i2s->mclk)) {
626 dev_err(&pdev->dev, "Can't retrieve i2s master clock\n");
627 ret = PTR_ERR(i2s->mclk);
637 i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
639 if (IS_ERR(i2s->regmap)) {
642 ret = PTR_ERR(i2s->regmap);
646 i2s->playback_dma_data.addr = res->start + I2S_TXDR;
647 i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
648 i2s->playback_dma_data.maxburst = 4;
650 i2s->capture_dma_data.addr = res->start + I2S_RXDR;
651 i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
652 i2s->capture_dma_data.maxburst = 4;
654 dev_set_drvdata(&pdev->dev, i2s);
703 clk_disable_unprepare(i2s->hclk);
709 struct rk_i2s_dev *i2s = dev_get_drvdata(&pdev->dev);
715 clk_disable_unprepare(i2s->hclk);