Lines Matching refs:pcfg
1236 union afe_port_config *pcfg = &port->port_cfg;
1238 pcfg->slim_cfg.sb_cfg_minor_version = AFE_API_VERSION_SLIMBUS_CONFIG;
1239 pcfg->slim_cfg.sample_rate = cfg->sample_rate;
1240 pcfg->slim_cfg.bit_width = cfg->bit_width;
1241 pcfg->slim_cfg.num_channels = cfg->num_channels;
1242 pcfg->slim_cfg.data_format = cfg->data_format;
1243 pcfg->slim_cfg.shared_ch_mapping[0] = cfg->ch_mapping[0];
1244 pcfg->slim_cfg.shared_ch_mapping[1] = cfg->ch_mapping[1];
1245 pcfg->slim_cfg.shared_ch_mapping[2] = cfg->ch_mapping[2];
1246 pcfg->slim_cfg.shared_ch_mapping[3] = cfg->ch_mapping[3];
1261 union afe_port_config *pcfg = &port->port_cfg;
1263 pcfg->tdm_cfg.tdm_cfg_minor_version = AFE_API_VERSION_TDM_CONFIG;
1264 pcfg->tdm_cfg.num_channels = cfg->num_channels;
1265 pcfg->tdm_cfg.sample_rate = cfg->sample_rate;
1266 pcfg->tdm_cfg.bit_width = cfg->bit_width;
1267 pcfg->tdm_cfg.data_format = cfg->data_format;
1268 pcfg->tdm_cfg.sync_mode = cfg->sync_mode;
1269 pcfg->tdm_cfg.sync_src = cfg->sync_src;
1270 pcfg->tdm_cfg.nslots_per_frame = cfg->nslots_per_frame;
1272 pcfg->tdm_cfg.slot_width = cfg->slot_width;
1273 pcfg->tdm_cfg.slot_mask = cfg->slot_mask;
1297 union afe_port_config *pcfg = &port->port_cfg;
1299 pcfg->hdmi_multi_ch.hdmi_cfg_minor_version =
1301 pcfg->hdmi_multi_ch.datatype = cfg->datatype;
1302 pcfg->hdmi_multi_ch.channel_allocation = cfg->channel_allocation;
1303 pcfg->hdmi_multi_ch.sample_rate = cfg->sample_rate;
1304 pcfg->hdmi_multi_ch.bit_width = cfg->bit_width;
1317 union afe_port_config *pcfg = &port->port_cfg;
1321 pcfg->i2s_cfg.i2s_cfg_minor_version = AFE_API_VERSION_I2S_CONFIG;
1322 pcfg->i2s_cfg.sample_rate = cfg->sample_rate;
1323 pcfg->i2s_cfg.bit_width = cfg->bit_width;
1324 pcfg->i2s_cfg.data_format = AFE_LINEAR_PCM_DATA;
1328 pcfg->i2s_cfg.ws_src = AFE_PORT_CONFIG_I2S_WS_SRC_INTERNAL;
1332 pcfg->i2s_cfg.ws_src = AFE_PORT_CONFIG_I2S_WS_SRC_EXTERNAL;
1347 pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_SD0;
1350 pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_SD1;
1353 pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_SD2;
1356 pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_SD3;
1366 pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_QUAD01;
1369 pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_QUAD23;
1379 pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_6CHS;
1389 pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_8CHS;
1405 switch (pcfg->i2s_cfg.channel_mode) {
1409 pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_SD0;
1412 pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_SD2;
1417 pcfg->i2s_cfg.mono_stereo = AFE_PORT_I2S_STEREO;
1419 pcfg->i2s_cfg.mono_stereo = AFE_PORT_I2S_MONO;
1424 if (pcfg->i2s_cfg.channel_mode < AFE_PORT_I2S_QUAD01) {
1431 if (pcfg->i2s_cfg.channel_mode < AFE_PORT_I2S_6CHS) {
1438 if (pcfg->i2s_cfg.channel_mode < AFE_PORT_I2S_8CHS) {
1461 union afe_port_config *pcfg = &port->port_cfg;
1462 struct afe_param_id_cdc_dma_cfg *dma_cfg = &pcfg->dma_cfg;