Lines Matching defs:SACR0
32 #define SACR0 __REG(0x40400000) /* Global Control Register */
105 SACR0 = 0;
176 if (!(SACR0 & SACR0_ENB)) {
177 SACR0 = 0;
179 SACR0 |= SACR0_BCKD;
181 SACR0 |= SACR0_RFTH(14) | SACR0_TFTH(1);
227 SACR0 |= SACR0_ENB;
254 SACR0 &= ~SACR0_ENB;
267 pxa_i2s.sacr0 = SACR0;
273 SACR0 &= ~SACR0_ENB;
282 SACR0 = pxa_i2s.sacr0 & ~SACR0_ENB;
287 SACR0 = pxa_i2s.sacr0;
305 * If SACR0[ENB] is toggled in the middle of a normal operation,
306 * the SACR0[RST] bit must also be set and cleared to reset all
309 SACR0 = SACR0_RST;
310 SACR0 = 0;