Lines Matching defs:master

34  * Each SAIF has a set of clock pins and can be operating in master
36 * Also, one of the two SAIFs can master or drive the clock pins while the
37 * other SAIF, in slave mode, receives clocking from the master SAIF.
40 * We abstract this as each saif has a master, the master could be
42 * to know the different clkmux. Saif only needs to know who is its master
43 * and operating its master to generate the proper clock rate for it.
44 * The master id is provided in mach-specific layer according to different
65 * is provided by other SAIF, we provide a interface here to get its master
67 * Note that the master could be itself.
87 /* Set master saif to generate proper clock */
92 dev_dbg(saif->dev, "master saif%d\n", master_saif->id);
97 "can not change clock, master saif%d(rate %d) is ongoing\n",
259 dev_err(saif->dev, "can not get mclk from a non-master saif\n");
355 * Note: We simply just support master mode since SAIF TX can only
356 * work as master.
357 * Here the master is relative to codec side.
540 dev_err(saif->dev, "Failed to enable master clock\n");
545 * If the saif's master is not itself, we also need to enable
551 dev_err(saif->dev, "Failed to enable master clock\n");
740 struct device_node *master;
758 * If there is no "fsl,saif-master" phandle, it's a saif
759 * master. Otherwise, it's a slave and its phandle points
760 * to the master.
762 master = of_parse_phandle(np, "fsl,saif-master", 0);
763 if (!master) {
766 ret = of_alias_get_id(master, "saif");
767 of_node_put(master);
774 dev_err(&pdev->dev, "get wrong master id\n");
807 /* We only support saif0 being tx and clock master */