Lines Matching refs:fifo
16 #include "axg-fifo.h"
20 * capture frontend DAI. The logic behind this two types of fifo is very
67 static void __dma_enable(struct axg_fifo *fifo, bool enable)
69 regmap_update_bits(fifo->map, FIFO_CTRL0, CTRL0_DMA_EN,
76 struct axg_fifo *fifo = axg_fifo_data(ss);
82 __dma_enable(fifo, true);
87 __dma_enable(fifo, false);
100 struct axg_fifo *fifo = axg_fifo_data(ss);
104 regmap_read(fifo->map, FIFO_STATUS2, &addr);
115 struct axg_fifo *fifo = axg_fifo_data(ss);
123 regmap_write(fifo->map, FIFO_START_ADDR, runtime->dma_addr);
124 regmap_write(fifo->map, FIFO_FINISH_ADDR, end_ptr);
128 regmap_write(fifo->map, FIFO_INT_ADDR, burst_num);
131 * Start the fifo request on the smallest of the following:
132 * - Half the fifo size
135 threshold = min(period / 2, fifo->depth / 2);
142 regmap_field_write(fifo->field_threshold,
146 regmap_update_bits(fifo->map, FIFO_CTRL0,
158 struct axg_fifo *fifo = axg_fifo_data(ss);
167 regmap_write(fifo->map, FIFO_INIT_ADDR, runtime->dma_addr);
176 struct axg_fifo *fifo = axg_fifo_data(ss);
179 regmap_update_bits(fifo->map, FIFO_CTRL0,
186 static void axg_fifo_ack_irq(struct axg_fifo *fifo, u8 mask)
188 regmap_update_bits(fifo->map, FIFO_CTRL1,
193 regmap_update_bits(fifo->map, FIFO_CTRL1,
201 struct axg_fifo *fifo = axg_fifo_data(ss);
204 regmap_read(fifo->map, FIFO_STATUS1, &status);
214 axg_fifo_ack_irq(fifo, status);
222 struct axg_fifo *fifo = axg_fifo_data(ss);
244 ret = request_irq(fifo->irq, axg_fifo_pcm_irq_block, 0,
249 /* Enable pclk to access registers and clock the fifo ip */
250 ret = clk_prepare_enable(fifo->pclk);
255 regmap_update_bits(fifo->map, FIFO_CTRL1,
260 __dma_enable(fifo, false);
263 regmap_update_bits(fifo->map, FIFO_CTRL0,
267 axg_fifo_ack_irq(fifo, FIFO_INT_MASK);
270 ret = reset_control_deassert(fifo->arb);
277 clk_disable_unprepare(fifo->pclk);
279 free_irq(fifo->irq, ss);
287 struct axg_fifo *fifo = axg_fifo_data(ss);
291 ret = reset_control_assert(fifo->arb);
293 /* Disable fifo ip and register access */
294 clk_disable_unprepare(fifo->pclk);
297 free_irq(fifo->irq, ss);
326 struct axg_fifo *fifo;
336 fifo = devm_kzalloc(dev, sizeof(*fifo), GFP_KERNEL);
337 if (!fifo)
339 platform_set_drvdata(pdev, fifo);
345 fifo->map = devm_regmap_init_mmio(dev, regs, &axg_fifo_regmap_cfg);
346 if (IS_ERR(fifo->map)) {
348 PTR_ERR(fifo->map));
349 return PTR_ERR(fifo->map);
352 fifo->pclk = devm_clk_get(dev, NULL);
353 if (IS_ERR(fifo->pclk)) {
354 if (PTR_ERR(fifo->pclk) != -EPROBE_DEFER)
356 PTR_ERR(fifo->pclk));
357 return PTR_ERR(fifo->pclk);
360 fifo->arb = devm_reset_control_get_exclusive(dev, NULL);
361 if (IS_ERR(fifo->arb)) {
362 if (PTR_ERR(fifo->arb) != -EPROBE_DEFER)
364 PTR_ERR(fifo->arb));
365 return PTR_ERR(fifo->arb);
368 fifo->irq = of_irq_get(dev->of_node, 0);
369 if (fifo->irq <= 0) {
370 dev_err(dev, "failed to get irq: %d\n", fifo->irq);
371 return fifo->irq;
374 fifo->field_threshold =
375 devm_regmap_field_alloc(dev, fifo->map, data->field_threshold);
376 if (IS_ERR(fifo->field_threshold))
377 return PTR_ERR(fifo->field_threshold);
379 ret = of_property_read_u32(dev->of_node, "amlogic,fifo-depth",
380 &fifo->depth);
387 * DT. In such case, assume the smallest known fifo depth
389 fifo->depth = 256;
390 dev_warn(dev, "fifo depth not found, assume %u bytes\n",
391 fifo->depth);
399 MODULE_DESCRIPTION("Amlogic AXG/G12A fifo driver");