Lines Matching refs:afe_priv
94 struct mt8183_afe_private *afe_priv = afe->platform_priv;
97 afe_priv->clk = devm_kcalloc(afe->dev, CLK_NUM, sizeof(*afe_priv->clk),
99 if (!afe_priv->clk)
103 afe_priv->clk[i] = devm_clk_get(afe->dev, aud_clks[i]);
104 if (IS_ERR(afe_priv->clk[i])) {
107 PTR_ERR(afe_priv->clk[i]));
108 return PTR_ERR(afe_priv->clk[i]);
117 struct mt8183_afe_private *afe_priv = afe->platform_priv;
120 ret = clk_prepare_enable(afe_priv->clk[CLK_INFRA_SYS_AUDIO]);
127 ret = clk_prepare_enable(afe_priv->clk[CLK_MUX_AUDIO]);
134 ret = clk_set_parent(afe_priv->clk[CLK_MUX_AUDIO],
135 afe_priv->clk[CLK_CLK26M]);
143 ret = clk_prepare_enable(afe_priv->clk[CLK_MUX_AUDIOINTBUS]);
150 ret = clk_set_parent(afe_priv->clk[CLK_MUX_AUDIOINTBUS],
151 afe_priv->clk[CLK_TOP_SYSPLL_D2_D4]);
159 ret = clk_prepare_enable(afe_priv->clk[CLK_AFE]);
166 ret = clk_prepare_enable(afe_priv->clk[CLK_I2S1_BCLK_SW]);
173 ret = clk_prepare_enable(afe_priv->clk[CLK_I2S2_BCLK_SW]);
180 ret = clk_prepare_enable(afe_priv->clk[CLK_I2S3_BCLK_SW]);
187 ret = clk_prepare_enable(afe_priv->clk[CLK_I2S4_BCLK_SW]);
197 clk_disable_unprepare(afe_priv->clk[CLK_I2S3_BCLK_SW]);
199 clk_disable_unprepare(afe_priv->clk[CLK_I2S2_BCLK_SW]);
201 clk_disable_unprepare(afe_priv->clk[CLK_I2S1_BCLK_SW]);
203 clk_disable_unprepare(afe_priv->clk[CLK_AFE]);
205 clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIOINTBUS]);
207 clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIO]);
209 clk_disable_unprepare(afe_priv->clk[CLK_INFRA_SYS_AUDIO]);
216 struct mt8183_afe_private *afe_priv = afe->platform_priv;
218 clk_disable_unprepare(afe_priv->clk[CLK_I2S4_BCLK_SW]);
219 clk_disable_unprepare(afe_priv->clk[CLK_I2S3_BCLK_SW]);
220 clk_disable_unprepare(afe_priv->clk[CLK_I2S2_BCLK_SW]);
221 clk_disable_unprepare(afe_priv->clk[CLK_I2S1_BCLK_SW]);
222 clk_disable_unprepare(afe_priv->clk[CLK_AFE]);
223 clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIOINTBUS]);
224 clk_disable_unprepare(afe_priv->clk[CLK_MUX_AUDIO]);
225 clk_disable_unprepare(afe_priv->clk[CLK_INFRA_SYS_AUDIO]);
233 struct mt8183_afe_private *afe_priv = afe->platform_priv;
237 ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_1]);
243 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1],
244 afe_priv->clk[CLK_TOP_APLL1_CK]);
253 ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1]);
259 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1],
260 afe_priv->clk[CLK_TOP_APLL1_D8]);
268 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1],
269 afe_priv->clk[CLK_CLK26M]);
276 clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1]);
278 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1],
279 afe_priv->clk[CLK_CLK26M]);
286 clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_1]);
292 clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1],
293 afe_priv->clk[CLK_CLK26M]);
294 clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_ENG1]);
297 clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1],
298 afe_priv->clk[CLK_CLK26M]);
299 clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_1]);
307 struct mt8183_afe_private *afe_priv = afe->platform_priv;
311 ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_2]);
317 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2],
318 afe_priv->clk[CLK_TOP_APLL2_CK]);
327 ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2]);
333 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2],
334 afe_priv->clk[CLK_TOP_APLL2_D8]);
342 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2],
343 afe_priv->clk[CLK_CLK26M]);
350 clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2]);
352 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2],
353 afe_priv->clk[CLK_CLK26M]);
360 clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_2]);
366 clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2],
367 afe_priv->clk[CLK_CLK26M]);
368 clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_ENG2]);
371 clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_2],
372 afe_priv->clk[CLK_CLK26M]);
373 clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_2]);
381 struct mt8183_afe_private *afe_priv = afe->platform_priv;
387 ret = clk_prepare_enable(afe_priv->clk[CLK_APLL22M]);
394 ret = clk_prepare_enable(afe_priv->clk[CLK_APLL1_TUNER]);
412 clk_disable_unprepare(afe_priv->clk[CLK_APLL22M]);
419 struct mt8183_afe_private *afe_priv = afe->platform_priv;
427 clk_disable_unprepare(afe_priv->clk[CLK_APLL1_TUNER]);
428 clk_disable_unprepare(afe_priv->clk[CLK_APLL22M]);
435 struct mt8183_afe_private *afe_priv = afe->platform_priv;
441 ret = clk_prepare_enable(afe_priv->clk[CLK_APLL24M]);
448 ret = clk_prepare_enable(afe_priv->clk[CLK_APLL2_TUNER]);
466 clk_disable_unprepare(afe_priv->clk[CLK_APLL24M]);
473 struct mt8183_afe_private *afe_priv = afe->platform_priv;
481 clk_disable_unprepare(afe_priv->clk[CLK_APLL2_TUNER]);
482 clk_disable_unprepare(afe_priv->clk[CLK_APLL24M]);
544 struct mt8183_afe_private *afe_priv = afe->platform_priv;
558 ret = clk_prepare_enable(afe_priv->clk[m_sel_id]);
564 ret = clk_set_parent(afe_priv->clk[m_sel_id],
565 afe_priv->clk[apll_clk_id]);
575 ret = clk_prepare_enable(afe_priv->clk[div_clk_id]);
581 ret = clk_set_rate(afe_priv->clk[div_clk_id], rate);
593 clk_disable_unprepare(afe_priv->clk[div_clk_id]);
597 clk_disable_unprepare(afe_priv->clk[m_sel_id]);
604 struct mt8183_afe_private *afe_priv = afe->platform_priv;
612 clk_disable_unprepare(afe_priv->clk[div_clk_id]);
614 clk_disable_unprepare(afe_priv->clk[m_sel_id]);