Lines Matching refs:base_ck
31 afe_priv->base_ck[i] = devm_clk_get(afe->dev, base_clks[i]);
32 if (IS_ERR(afe_priv->base_ck[i])) {
34 return PTR_ERR(afe_priv->base_ck[i]);
171 ret = clk_prepare_enable(afe_priv->base_ck[MT2701_INFRA_SYS_AUDIO]);
176 ret = clk_prepare_enable(afe_priv->base_ck[MT2701_TOP_AUD_A1SYS]);
181 ret = clk_prepare_enable(afe_priv->base_ck[MT2701_TOP_AUD_A2SYS]);
186 ret = clk_prepare_enable(afe_priv->base_ck[MT2701_AUDSYS_AFE]);
190 ret = clk_prepare_enable(afe_priv->base_ck[MT2701_AUDSYS_A1SYS]);
194 ret = clk_prepare_enable(afe_priv->base_ck[MT2701_AUDSYS_A2SYS]);
198 ret = clk_prepare_enable(afe_priv->base_ck[MT2701_AUDSYS_AFE_CONN]);
205 clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_A2SYS]);
207 clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_A1SYS]);
209 clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_AFE]);
211 clk_disable_unprepare(afe_priv->base_ck[MT2701_TOP_AUD_A2SYS]);
213 clk_disable_unprepare(afe_priv->base_ck[MT2701_TOP_AUD_A1SYS]);
215 clk_disable_unprepare(afe_priv->base_ck[MT2701_INFRA_SYS_AUDIO]);
224 clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_AFE_CONN]);
225 clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_A2SYS]);
226 clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_A1SYS]);
227 clk_disable_unprepare(afe_priv->base_ck[MT2701_AUDSYS_AFE]);
228 clk_disable_unprepare(afe_priv->base_ck[MT2701_TOP_AUD_A1SYS]);
229 clk_disable_unprepare(afe_priv->base_ck[MT2701_TOP_AUD_A2SYS]);
230 clk_disable_unprepare(afe_priv->base_ck[MT2701_INFRA_SYS_AUDIO]);
280 priv->base_ck[MT2701_TOP_AUD_MCLK_SRC0]);
283 priv->base_ck[MT2701_TOP_AUD_MCLK_SRC1]);