Lines Matching defs:ret
105 int ret;
107 ret = clk_prepare_enable(i2s_path->asrco_ck);
108 if (ret) {
109 dev_err(afe->dev, "failed to enable ASRC clock %d\n", ret);
110 return ret;
113 ret = clk_prepare_enable(i2s_path->hop_ck[dir]);
114 if (ret) {
115 dev_err(afe->dev, "failed to enable I2S clock %d\n", ret);
124 return ret;
168 int ret;
171 ret = clk_prepare_enable(afe_priv->base_ck[MT2701_INFRA_SYS_AUDIO]);
172 if (ret)
173 return ret;
176 ret = clk_prepare_enable(afe_priv->base_ck[MT2701_TOP_AUD_A1SYS]);
177 if (ret)
181 ret = clk_prepare_enable(afe_priv->base_ck[MT2701_TOP_AUD_A2SYS]);
182 if (ret)
186 ret = clk_prepare_enable(afe_priv->base_ck[MT2701_AUDSYS_AFE]);
187 if (ret)
190 ret = clk_prepare_enable(afe_priv->base_ck[MT2701_AUDSYS_A1SYS]);
191 if (ret)
194 ret = clk_prepare_enable(afe_priv->base_ck[MT2701_AUDSYS_A2SYS]);
195 if (ret)
198 ret = clk_prepare_enable(afe_priv->base_ck[MT2701_AUDSYS_AFE_CONN]);
199 if (ret)
217 return ret;
235 int ret;
238 ret = mt2701_afe_enable_audsys(afe);
239 if (ret) {
240 dev_err(afe->dev, "failed to enable audio system %d\n", ret);
241 return ret;
275 int ret = -EINVAL;
279 ret = clk_set_parent(i2s_path->sel_ck,
282 ret = clk_set_parent(i2s_path->sel_ck,
285 if (ret) {
287 return ret;
291 ret = clk_set_rate(i2s_path->div_ck, i2s_path->mclk_rate);
292 if (ret) {
293 dev_err(afe->dev, "failed to set mclk divider %d\n", ret);
294 return ret;