Lines Matching refs:ctx
17 static void skl_cldma_int_enable(struct sst_dsp *ctx)
19 sst_dsp_shim_update_bits_unlocked(ctx, SKL_ADSP_REG_ADSPIC,
23 void skl_cldma_int_disable(struct sst_dsp *ctx)
25 sst_dsp_shim_update_bits_unlocked(ctx,
29 static void skl_cldma_stream_run(struct sst_dsp *ctx, bool enable)
34 sst_dsp_shim_update_bits_unlocked(ctx,
42 val = sst_dsp_shim_read(ctx, SKL_ADSP_REG_CL_SD_CTL) &
52 dev_err(ctx->dev, "Failed to set Run bit=%d enable=%d\n", val, enable);
55 static void skl_cldma_stream_clear(struct sst_dsp *ctx)
58 skl_cldma_stream_run(ctx, 0);
60 sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
62 sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
64 sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
66 sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
69 sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_BDLPL, CL_SD_BDLPLBA(0));
70 sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_BDLPU, 0);
72 sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_CBL, 0);
73 sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_LVI, 0);
77 static void skl_cldma_setup_bdle(struct sst_dsp *ctx,
83 ctx->cl_dev.frags = 0;
86 (ctx->cl_dev.frags * ctx->cl_dev.bufsize));
91 bdl[2] = cpu_to_le32(ctx->cl_dev.bufsize);
93 size -= ctx->cl_dev.bufsize;
97 ctx->cl_dev.frags++;
107 static void skl_cldma_setup_controller(struct sst_dsp *ctx,
111 skl_cldma_stream_clear(ctx);
112 sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_BDLPL,
114 sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_BDLPU,
117 sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_CBL, max_size);
118 sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_LVI, count - 1);
119 sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
121 sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
123 sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
125 sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
129 static void skl_cldma_setup_spb(struct sst_dsp *ctx,
133 sst_dsp_shim_update_bits_unlocked(ctx,
138 sst_dsp_shim_write_unlocked(ctx, SKL_ADSP_REG_CL_SPBFIFO_SPIB, size);
141 static void skl_cldma_cleanup_spb(struct sst_dsp *ctx)
143 sst_dsp_shim_update_bits_unlocked(ctx,
148 sst_dsp_shim_write_unlocked(ctx, SKL_ADSP_REG_CL_SPBFIFO_SPIB, 0);
151 static void skl_cldma_cleanup(struct sst_dsp *ctx)
153 skl_cldma_cleanup_spb(ctx);
154 skl_cldma_stream_clear(ctx);
156 ctx->dsp_ops.free_dma_buf(ctx->dev, &ctx->cl_dev.dmab_data);
157 ctx->dsp_ops.free_dma_buf(ctx->dev, &ctx->cl_dev.dmab_bdl);
160 int skl_cldma_wait_interruptible(struct sst_dsp *ctx)
164 if (!wait_event_timeout(ctx->cl_dev.wait_queue,
165 ctx->cl_dev.wait_condition,
167 dev_err(ctx->dev, "%s: Wait timeout\n", __func__);
172 dev_dbg(ctx->dev, "%s: Event wake\n", __func__);
173 if (ctx->cl_dev.wake_status != SKL_CL_DMA_BUF_COMPLETE) {
174 dev_err(ctx->dev, "%s: DMA Error\n", __func__);
179 ctx->cl_dev.wake_status = SKL_CL_DMA_STATUS_NONE;
183 static void skl_cldma_stop(struct sst_dsp *ctx)
185 skl_cldma_stream_run(ctx, false);
188 static void skl_cldma_fill_buffer(struct sst_dsp *ctx, unsigned int size,
191 dev_dbg(ctx->dev, "Size: %x, intr_enable: %d\n", size, intr_enable);
192 dev_dbg(ctx->dev, "buf_pos_index:%d, trigger:%d\n",
193 ctx->cl_dev.dma_buffer_offset, trigger);
194 dev_dbg(ctx->dev, "spib position: %d\n", ctx->cl_dev.curr_spib_pos);
201 if (ctx->cl_dev.dma_buffer_offset + size > ctx->cl_dev.bufsize) {
202 unsigned int size_b = ctx->cl_dev.bufsize -
203 ctx->cl_dev.dma_buffer_offset;
204 memcpy(ctx->cl_dev.dmab_data.area + ctx->cl_dev.dma_buffer_offset,
208 ctx->cl_dev.dma_buffer_offset = 0;
211 memcpy(ctx->cl_dev.dmab_data.area + ctx->cl_dev.dma_buffer_offset,
214 if (ctx->cl_dev.curr_spib_pos == ctx->cl_dev.bufsize)
215 ctx->cl_dev.dma_buffer_offset = 0;
217 ctx->cl_dev.dma_buffer_offset = ctx->cl_dev.curr_spib_pos;
219 ctx->cl_dev.wait_condition = false;
222 skl_cldma_int_enable(ctx);
224 ctx->cl_dev.ops.cl_setup_spb(ctx, ctx->cl_dev.curr_spib_pos, trigger);
226 ctx->cl_dev.ops.cl_trigger(ctx, true);
245 skl_cldma_copy_to_buf(struct sst_dsp *ctx, const void *bin,
258 dev_dbg(ctx->dev, "%s: Total binary size: %u\n", __func__, bytes_left);
261 if (bytes_left > ctx->cl_dev.bufsize) {
267 if (ctx->cl_dev.curr_spib_pos == 0)
268 ctx->cl_dev.curr_spib_pos = ctx->cl_dev.bufsize;
270 size = ctx->cl_dev.bufsize;
271 skl_cldma_fill_buffer(ctx, size, curr_pos, true, start);
275 ret = skl_cldma_wait_interruptible(ctx);
277 skl_cldma_stop(ctx);
282 skl_cldma_int_disable(ctx);
284 if ((ctx->cl_dev.curr_spib_pos + bytes_left)
285 <= ctx->cl_dev.bufsize) {
286 ctx->cl_dev.curr_spib_pos += bytes_left;
289 (ctx->cl_dev.bufsize -
290 ctx->cl_dev.curr_spib_pos);
291 ctx->cl_dev.curr_spib_pos = excess_bytes;
295 skl_cldma_fill_buffer(ctx, size,
307 void skl_cldma_process_intr(struct sst_dsp *ctx)
312 sst_dsp_shim_read_unlocked(ctx, SKL_ADSP_REG_CL_SD_STS);
315 ctx->cl_dev.wake_status = SKL_CL_DMA_ERR;
317 ctx->cl_dev.wake_status = SKL_CL_DMA_BUF_COMPLETE;
319 ctx->cl_dev.wait_condition = true;
320 wake_up(&ctx->cl_dev.wait_queue);
323 int skl_cldma_prepare(struct sst_dsp *ctx)
328 ctx->cl_dev.bufsize = SKL_MAX_BUFFER_SIZE;
331 ctx->cl_dev.ops.cl_setup_bdle = skl_cldma_setup_bdle;
332 ctx->cl_dev.ops.cl_setup_controller = skl_cldma_setup_controller;
333 ctx->cl_dev.ops.cl_setup_spb = skl_cldma_setup_spb;
334 ctx->cl_dev.ops.cl_cleanup_spb = skl_cldma_cleanup_spb;
335 ctx->cl_dev.ops.cl_trigger = skl_cldma_stream_run;
336 ctx->cl_dev.ops.cl_cleanup_controller = skl_cldma_cleanup;
337 ctx->cl_dev.ops.cl_copy_to_dmabuf = skl_cldma_copy_to_buf;
338 ctx->cl_dev.ops.cl_stop_dma = skl_cldma_stop;
341 ret = ctx->dsp_ops.alloc_dma_buf(ctx->dev,
342 &ctx->cl_dev.dmab_data, ctx->cl_dev.bufsize);
344 dev_err(ctx->dev, "Alloc buffer for base fw failed: %x\n", ret);
348 ret = ctx->dsp_ops.alloc_dma_buf(ctx->dev,
349 &ctx->cl_dev.dmab_bdl, PAGE_SIZE);
351 dev_err(ctx->dev, "Alloc buffer for blde failed: %x\n", ret);
352 ctx->dsp_ops.free_dma_buf(ctx->dev, &ctx->cl_dev.dmab_data);
355 bdl = (__le32 *)ctx->cl_dev.dmab_bdl.area;
358 ctx->cl_dev.ops.cl_setup_bdle(ctx, &ctx->cl_dev.dmab_data,
359 &bdl, ctx->cl_dev.bufsize, 1);
360 ctx->cl_dev.ops.cl_setup_controller(ctx, &ctx->cl_dev.dmab_bdl,
361 ctx->cl_dev.bufsize, ctx->cl_dev.frags);
363 ctx->cl_dev.curr_spib_pos = 0;
364 ctx->cl_dev.dma_buffer_offset = 0;
365 init_waitqueue_head(&ctx->cl_dev.wait_queue);