Lines Matching refs:cl_dev
83 ctx->cl_dev.frags = 0;
86 (ctx->cl_dev.frags * ctx->cl_dev.bufsize));
91 bdl[2] = cpu_to_le32(ctx->cl_dev.bufsize);
93 size -= ctx->cl_dev.bufsize;
97 ctx->cl_dev.frags++;
156 ctx->dsp_ops.free_dma_buf(ctx->dev, &ctx->cl_dev.dmab_data);
157 ctx->dsp_ops.free_dma_buf(ctx->dev, &ctx->cl_dev.dmab_bdl);
164 if (!wait_event_timeout(ctx->cl_dev.wait_queue,
165 ctx->cl_dev.wait_condition,
173 if (ctx->cl_dev.wake_status != SKL_CL_DMA_BUF_COMPLETE) {
179 ctx->cl_dev.wake_status = SKL_CL_DMA_STATUS_NONE;
193 ctx->cl_dev.dma_buffer_offset, trigger);
194 dev_dbg(ctx->dev, "spib position: %d\n", ctx->cl_dev.curr_spib_pos);
201 if (ctx->cl_dev.dma_buffer_offset + size > ctx->cl_dev.bufsize) {
202 unsigned int size_b = ctx->cl_dev.bufsize -
203 ctx->cl_dev.dma_buffer_offset;
204 memcpy(ctx->cl_dev.dmab_data.area + ctx->cl_dev.dma_buffer_offset,
208 ctx->cl_dev.dma_buffer_offset = 0;
211 memcpy(ctx->cl_dev.dmab_data.area + ctx->cl_dev.dma_buffer_offset,
214 if (ctx->cl_dev.curr_spib_pos == ctx->cl_dev.bufsize)
215 ctx->cl_dev.dma_buffer_offset = 0;
217 ctx->cl_dev.dma_buffer_offset = ctx->cl_dev.curr_spib_pos;
219 ctx->cl_dev.wait_condition = false;
224 ctx->cl_dev.ops.cl_setup_spb(ctx, ctx->cl_dev.curr_spib_pos, trigger);
226 ctx->cl_dev.ops.cl_trigger(ctx, true);
261 if (bytes_left > ctx->cl_dev.bufsize) {
267 if (ctx->cl_dev.curr_spib_pos == 0)
268 ctx->cl_dev.curr_spib_pos = ctx->cl_dev.bufsize;
270 size = ctx->cl_dev.bufsize;
284 if ((ctx->cl_dev.curr_spib_pos + bytes_left)
285 <= ctx->cl_dev.bufsize) {
286 ctx->cl_dev.curr_spib_pos += bytes_left;
289 (ctx->cl_dev.bufsize -
290 ctx->cl_dev.curr_spib_pos);
291 ctx->cl_dev.curr_spib_pos = excess_bytes;
315 ctx->cl_dev.wake_status = SKL_CL_DMA_ERR;
317 ctx->cl_dev.wake_status = SKL_CL_DMA_BUF_COMPLETE;
319 ctx->cl_dev.wait_condition = true;
320 wake_up(&ctx->cl_dev.wait_queue);
328 ctx->cl_dev.bufsize = SKL_MAX_BUFFER_SIZE;
331 ctx->cl_dev.ops.cl_setup_bdle = skl_cldma_setup_bdle;
332 ctx->cl_dev.ops.cl_setup_controller = skl_cldma_setup_controller;
333 ctx->cl_dev.ops.cl_setup_spb = skl_cldma_setup_spb;
334 ctx->cl_dev.ops.cl_cleanup_spb = skl_cldma_cleanup_spb;
335 ctx->cl_dev.ops.cl_trigger = skl_cldma_stream_run;
336 ctx->cl_dev.ops.cl_cleanup_controller = skl_cldma_cleanup;
337 ctx->cl_dev.ops.cl_copy_to_dmabuf = skl_cldma_copy_to_buf;
338 ctx->cl_dev.ops.cl_stop_dma = skl_cldma_stop;
342 &ctx->cl_dev.dmab_data, ctx->cl_dev.bufsize);
349 &ctx->cl_dev.dmab_bdl, PAGE_SIZE);
352 ctx->dsp_ops.free_dma_buf(ctx->dev, &ctx->cl_dev.dmab_data);
355 bdl = (__le32 *)ctx->cl_dev.dmab_bdl.area;
358 ctx->cl_dev.ops.cl_setup_bdle(ctx, &ctx->cl_dev.dmab_data,
359 &bdl, ctx->cl_dev.bufsize, 1);
360 ctx->cl_dev.ops.cl_setup_controller(ctx, &ctx->cl_dev.dmab_bdl,
361 ctx->cl_dev.bufsize, ctx->cl_dev.frags);
363 ctx->cl_dev.curr_spib_pos = 0;
364 ctx->cl_dev.dma_buffer_offset = 0;
365 init_waitqueue_head(&ctx->cl_dev.wait_queue);